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GET /api/patches/2195142/?format=api
{ "id": 2195142, "url": "http://patchwork.ozlabs.org/api/patches/2195142/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134647.2050821-4-calebs@linux.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210134647.2050821-4-calebs@linux.ibm.com>", "list_archive_url": null, "date": "2026-02-10T13:46:47", "name": "[v2,3/3] ppc/pnv: Add OCC FLAG registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d17cfee89a59f6b3fbea7b68975c1ebd912d9a02", "submitter": { "id": 90855, "url": "http://patchwork.ozlabs.org/api/people/90855/?format=api", "name": "Caleb Schlossin", "email": "calebs@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134647.2050821-4-calebs@linux.ibm.com/mbox/", "series": [ { "id": 491679, "url": "http://patchwork.ozlabs.org/api/series/491679/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491679", "date": "2026-02-10T13:46:47", "name": "Power10 PowerVM bringup fixes", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491679/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195142/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195142/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n 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:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=pp1; bh=cdBVwGCxSnxrDjWE2\n y41YmM3oFnGfVhqTyW79zwjnm4=; b=UR6kNHqtXJnnPz1DZ6gHzFOI9EXOA9GEP\n wIoXRfUAmgfbOzk3Hmwx7udbIkxdIOzsFb1elDndCnL2Xq6YdeKcqgBWTwCa5UnV\n GapyHAThL+bNsfmYRwEYFEVa31hItUU5LjQVUuSoSgPBfjS9ZBVe6ly1gbE+4iF3\n PhEntCL+b0xENCNvhEl/OuHwKx/Pr/qg1qVpsQx4RSbz0GPRoLi87+nxzWrXqsOG\n rWZ6NN9lNTBICfKjKbeSUBm5/c4ArhRuhGI7Dqy4EuuRBFx8LYzZ70GwQk37qv/F\n UkP+150X8Y3vLkedHkPuptV6KNhQCoW63Bt9ihlqe9ixlL43KRlnA==", "From": "Caleb Schlossin <calebs@linux.ibm.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-ppc@nongnu.org, npiggin@gmail.com, adityag@linux.ibm.com,\n milesg@linux.ibm.com, chalapathi.v@linux.ibm.com,\n harshpb@linux.ibm.com, calebs@linux.ibm.com", "Subject": "[PATCH v2 3/3] ppc/pnv: Add OCC FLAG registers", "Date": "Tue, 10 Feb 2026 07:46:47 -0600", "Message-ID": "<20260210134647.2050821-4-calebs@linux.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": 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"X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "OCCFLG are scratch registers that can be shared with OCC firmware.\nLog reads and writes to the registers as a reminder when we run\ninto more OCC code.\n\nAdd RW, WO_CLEAR and WO_OR SCOM Type enums in pnv_occ.c\n\nReviewed-by: Chalapathi V <chalapathi.v@linux.ibm.com\nReviewed-by: Glenn Miles <milesg@linux.ibm.com>\nReviewed-by: Aditya Gupta <adityag@linux.ibm.com>\nSigned-off-by: Chalapathi V <chalapathi.v@linux.ibm.com>\nSigned-off-by: Caleb Schlossin <calebs@linux.ibm.com>\n---\n hw/ppc/pnv_occ.c | 55 +++++++++++++++++++++++++++++++++++++---\n include/hw/ppc/pnv_occ.h | 4 +++\n 2 files changed, 56 insertions(+), 3 deletions(-)", "diff": "diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c\nindex 64cab3e9dc..b9f69daffc 100644\n--- a/hw/ppc/pnv_occ.c\n+++ b/hw/ppc/pnv_occ.c\n@@ -195,6 +195,49 @@ static const TypeInfo pnv_occ_power8_type_info = {\n #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081\n #define P9_OCB_OCI_OCCMISC_OR 0x6082\n \n+/* OCC scratch registers for flag setting */\n+#define P9_OCCFLG0 0x60ac\n+#define P9_OCCFLG7_OR 0x60c3\n+\n+enum ScomType {\n+ SCOM_TYPE_RW = 0,\n+ SCOM_TYPE_WO_CLEAR = 1,\n+ SCOM_TYPE_WO_OR = 2,\n+};\n+\n+static void rw_occ_flag_regs(PnvOCC *occ, uint32_t offset, bool read,\n+ uint64_t *val)\n+{\n+ int flag_num;\n+ int flag_type;\n+\n+ /*\n+ * Each OCCFLG register has SCOM0 - RW, SCOM1 - WO_CLEAR, SCOM2 - WO_OR\n+ * hence divide by 3 to get flag index and mod 3 to get SCOM type.\n+ */\n+ flag_num = (offset - P9_OCCFLG0) / 3;\n+ flag_type = (offset - P9_OCCFLG0) % 3;\n+\n+ if (read) {\n+ if (flag_type) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"OCC: Write only register: Ox%\"\n+ PRIx32 \"\\n\", offset);\n+ return;\n+ }\n+ *val = occ->occflags[flag_num];\n+ } else {\n+ switch (flag_type) {\n+ case SCOM_TYPE_RW:\n+ occ->occflags[flag_num] = *val;\n+ break;\n+ case SCOM_TYPE_WO_CLEAR:\n+ occ->occflags[flag_num] &= ~(*val);\n+ break;\n+ case SCOM_TYPE_WO_OR:\n+ occ->occflags[flag_num] |= *val;\n+ }\n+ }\n+}\n \n static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,\n unsigned size)\n@@ -207,8 +250,11 @@ static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,\n case P9_OCB_OCI_OCCMISC:\n val = occ->occmisc;\n break;\n+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:\n+ rw_occ_flag_regs(occ, offset, 1, &val);\n+ break;\n default:\n- qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register: Ox%\"\n+ qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register read: Ox%\"\n HWADDR_PRIx \"\\n\", addr >> 3);\n }\n return val;\n@@ -229,9 +275,12 @@ static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,\n break;\n case P9_OCB_OCI_OCCMISC:\n pnv_occ_set_misc(occ, val);\n- break;\n+ break;\n+ case P9_OCCFLG0 ... P9_OCCFLG7_OR:\n+ rw_occ_flag_regs(occ, offset, 0, &val);\n+ break;\n default:\n- qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register: Ox%\"\n+ qemu_log_mask(LOG_UNIMP, \"OCC Unimplemented register write: Ox%\"\n HWADDR_PRIx \"\\n\", addr >> 3);\n }\n }\ndiff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h\nindex 84bdf5004d..92a4dbf1a0 100644\n--- a/include/hw/ppc/pnv_occ.h\n+++ b/include/hw/ppc/pnv_occ.h\n@@ -47,6 +47,10 @@ struct PnvOCC {\n /* OCC Misc interrupt */\n uint64_t occmisc;\n \n+ /* OCC Flags */\n+#define NR_FLAG_REGS 8\n+ uint32_t occflags[NR_FLAG_REGS];\n+\n qemu_irq psi_irq;\n \n /* OCCs operate on regions of HOMER memory */\n", "prefixes": [ "v2", "3/3" ] }