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GET /api/patches/2195140/?format=api
{ "id": 2195140, "url": "http://patchwork.ozlabs.org/api/patches/2195140/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-5-saif.abrar@linux.vnet.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210134110.1515322-5-saif.abrar@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2026-02-10T13:40:54", "name": "[v3,4/9] pnv/phb4: Implement read-only and write-only bits of registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "df49528d84d84a3ea5f45a276b51d401a426e1bd", "submitter": { "id": 87200, "url": "http://patchwork.ozlabs.org/api/people/87200/?format=api", "name": "Saif Abrar", "email": "saif.abrar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-5-saif.abrar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 491677, "url": "http://patchwork.ozlabs.org/api/series/491677/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491677", "date": "2026-02-10T13:40:52", "name": ": pnv/phb4: Update PHB4 to the latest PHB5 spec", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491677/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195140/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195140/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=Qh+PKKBj;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pp1; bh=S4shNQ\n N9fwoS+DqjKLjVhjAhPZKpz3Pq55hbYoR/o00=; b=Qh+PKKBjiPqBGwg1SuL7Kz\n HWXWWJy5Co1YO59By0JlSiEz/1JYgJBgpL1uS8i13WhO05U/dRWIp73jcEGFn3HG\n /l4QxH+85qyzKy1+5It0k7FYfd3xMBwJ/YFR/UN8RLkbaZefZq1cV/vTrQ4HclAO\n WmMwAy+OesRh2NtRBWOnEAXrvjSeQO83tU7A0v/diOS/4q04E0NVp16sAuo5e/Xz\n KuMRMt9IGtg7gy6ngPqwdobN4TI0TKtwNrH4J3Do7g04uUpLBnGZeLu8InJGDoN2\n 1pIzUNhe09RoPSHaDm4/fzCCSj2eLDLG5sIJH/Ci5+iTKwj4JQfIKKTD9CCn/grw\n ==", "From": "Saif Abrar <saif.abrar@linux.vnet.ibm.com>", "To": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org", "Cc": "clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com,\n marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com,\n thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com,\n saif.abrar@linux.vnet.ibm.com", "Subject": "[PATCH v3 4/9] pnv/phb4: Implement read-only and write-only bits of\n registers", "Date": "Tue, 10 Feb 2026 07:40:54 -0600", "Message-ID": "<20260210134110.1515322-5-saif.abrar@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "References": "<20251230102156.886288-1-saif.abrar@linux.vnet.ibm.com>\n <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-Reinject": "loops=2 maxloops=12", "X-Authority-Analysis": "v=2.4 cv=YZiwJgRf c=1 sm=1 tr=0 ts=698b35ac cx=c_pps\n a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VnNF1IyMAAAA:8\n a=aow-egSQAAAA:8 a=20KFwNOVAAAA:8 a=mfz1QdnSRwmfuQrPUawA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=gFNbaldVC-z-bsjSTzMo:22", "X-Proofpoint-ORIG-GUID": "fV-kleKN3AKfDlzc7FvPbjdIbz8N_Nfc", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEwMDExMiBTYWx0ZWRfX2mny80u27hoc\n qRxjiOj1v+S5p7xStG3n7CITkAW1MjEUX+nCGCTk5Cir5PESsd7fRmG5zaHS+wg/dA6u+uanrEz\n cpyPXGgmeNF9UTgDEG1Wbe47Axu9Oy05H5HrujLknbvWsnWXJ7Ez+vnSVl3UXWuqkvFJySYV0vk\n EJagGwNTTcZrl1Ijvfgl6Gg3yTePmDENBVHleDrb7mdjV/03lAzqocQll6Kf758wcstBquhc7hu\n NxGB6FXqRFVGw07sWRVGLkRcv8gdRKe9w9qFnelpbbxnsJMOQNI93f2Jq/w5jxWXyhzde7H8usQ\n cA/Dfq9ampy7HgG1EdtIxGpw0DU/ncpuROaia0z9wTjzN9UVlIh3lQhd+BZcdjyP7k1xeIMFM6k\n vTCDWST01qx8yYrbx92yyyWuL2v4tm3veDoh62Q+wA5QVz9+S4c1R5yRKGUVBpKMMQ8IOgZZJsK\n cEAWAO4UHJ8JxuPWFSA==", "X-Proofpoint-GUID": "rYvPEaYe9_4y4z-ldt70eD54nIpFcxrA", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-10_01,2026-02-10_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 malwarescore=0\n phishscore=0 bulkscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602100112", "Received-SPF": "none client-ip=148.163.156.1;\n envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "SW cannot write the read-only(RO) bits of a register\nand write-only(WO) bits of a register return 0 when read.\n\nAdded ro_mask[] for each register that defines which\nbits in that register are RO.\nWhen writing to a register, the RO-bits are not updated.\n\nWhen reading a register, clear the WO bits and return the updated value.\n\nTested the registers PHB_DMA_SYNC, PHB_PCIE_HOTPLUG_STATUS, PHB_PCIE_LMR,\nPHB_PCIE_DLP_TRWCTL, PHB_LEM_ERROR_AND_MASK and PHB_LEM_ERROR_OR_MASK\nby writing all 1's and reading back the value.\nThe WO bits in these registers should read back as 0.\n\nAdded .class_size in pnv_phb4_type_info for PnvPHB4Class.\n\nSigned-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>\nReviewed-by: Cédric Le Goater <clg@kaod.org>\nReviewed-by: \"Michael S. Tsirkin\" <mst@redhat.com>\n---\nv3:\n- Updates for coding guidelines.\n- Added class size for PnvPHB4Class.\n\nv2: New PnvPHB4Class to hold each register's RO mask.\n\n hw/pci-host/pnv_phb4.c | 80 ++++++++++++++++++++++++++---\n include/hw/pci-host/pnv_phb4.h | 13 ++++-\n include/hw/pci-host/pnv_phb4_regs.h | 20 ++++++--\n tests/qtest/pnv-phb4-test.c | 60 +++++++++++++++++++++-\n 4 files changed, 159 insertions(+), 14 deletions(-)", "diff": "diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c\nindex 961888e952..07479346c2 100644\n--- a/hw/pci-host/pnv_phb4.c\n+++ b/hw/pci-host/pnv_phb4.c\n@@ -706,6 +706,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n return;\n }\n \n+ /* Update 'val' according to the register's RO-mask */\n+ PnvPHB4Class *k = PNV_PHB4_GET_CLASS(phb);\n+\n+ val = (phb->regs[off >> 3] & k->ro_mask[off >> 3]) |\n+ (val & ~(k->ro_mask[off >> 3]));\n+\n /* Record whether it changed */\n changed = phb->regs[off >> 3] != val;\n \n@@ -781,7 +787,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n case PHB_TCE_TAG_ENABLE:\n case PHB_INT_NOTIFY_ADDR:\n case PHB_INT_NOTIFY_INDEX:\n- case PHB_DMARD_SYNC:\n+ case PHB_DMA_SYNC:\n break;\n \n /* Noise on anything else */\n@@ -819,7 +825,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)\n case PHB_VERSION:\n return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version;\n \n- /* Read-only */\n+ /* Read-only */\n case PHB_PHB4_GEN_CAP:\n return 0xe4b8000000000000ull;\n case PHB_PHB4_TCE_CAP:\n@@ -829,18 +835,49 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)\n case PHB_PHB4_EEH_CAP:\n return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull;\n \n+ /* Write-only, read will return zeros */\n+ case PHB_LEM_ERROR_AND_MASK:\n+ case PHB_LEM_ERROR_OR_MASK:\n+ return 0;\n+ case PHB_PCIE_DLP_TRWCTL:\n+ val &= ~PHB_PCIE_DLP_TRWCTL_WREN;\n+ return val;\n /* IODA table accesses */\n case PHB_IODA_DATA0:\n return pnv_phb4_ioda_read(phb);\n \n+ /*\n+ * DMA sync: make it look like it's complete,\n+ * clear write-only read/write start sync bits.\n+ */\n+ case PHB_DMA_SYNC:\n+ val = PHB_DMA_SYNC_RD_COMPLETE |\n+ ~(PHB_DMA_SYNC_RD_START | PHB_DMA_SYNC_WR_START);\n+ return val;\n+\n+ /*\n+ * PCI-E Stack registers\n+ */\n+ case PHB_PCIE_SCR:\n+ val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */\n+ break;\n+\n /* Link training always appears trained */\n case PHB_PCIE_DLP_TRAIN_CTL:\n /* TODO: Do something sensible with speed ? */\n- return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;\n+ val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;\n+ return val;\n \n- /* DMA read sync: make it look like it's complete */\n- case PHB_DMARD_SYNC:\n- return PHB_DMARD_SYNC_COMPLETE;\n+ case PHB_PCIE_HOTPLUG_STATUS:\n+ /* Clear write-only bit */\n+ val &= ~PHB_PCIE_HPSTAT_RESAMPLE;\n+ return val;\n+\n+ /* Link Management Register */\n+ case PHB_PCIE_LMR:\n+ /* These write-only bits always read as 0 */\n+ val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK);\n+ return val;\n \n /* Silent simple reads */\n case PHB_LSI_SOURCE_ID:\n@@ -1685,6 +1722,32 @@ static PCIIOMMUOps pnv_phb4_iommu_ops = {\n .get_address_space = pnv_phb4_dma_iommu,\n };\n \n+static void pnv_phb4_ro_mask_init(PnvPHB4 *phb)\n+{\n+ PnvPHB4Class *phb4c = PNV_PHB4_GET_CLASS(phb);\n+\n+ /*\n+ * Set register specific RO-masks\n+ */\n+\n+ /* PBL - Error Injection Register (0x1910) */\n+ phb4c->ro_mask[PHB_PBL_ERR_INJECT >> 3] =\n+ PPC_BITMASK(0, 23) | PPC_BITMASK(28, 35) | PPC_BIT(38) | PPC_BIT(46) |\n+ PPC_BITMASK(49, 51) | PPC_BITMASK(55, 63);\n+\n+ /* Reserved bits[60:63] */\n+ phb4c->ro_mask[PHB_TXE_ERR_LEM_ENABLE >> 3] =\n+ phb4c->ro_mask[PHB_TXE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(60, 63);\n+ /* Reserved bits[36:63] */\n+ phb4c->ro_mask[PHB_RXE_TCE_ERR_LEM_ENABLE >> 3] =\n+ phb4c->ro_mask[PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(36, 63);\n+ /* Reserved bits[40:63] */\n+ phb4c->ro_mask[PHB_ERR_LEM_ENABLE >> 3] =\n+ phb4c->ro_mask[PHB_ERR_AIB_FENCE_ENABLE >> 3] = PPC_BITMASK(40, 63);\n+\n+ /* TODO: Add more RO-masks as regs are implemented in the model */\n+}\n+\n static void pnv_phb4_err_reg_reset(PnvPHB4 *phb)\n {\n STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33));\n@@ -1744,6 +1807,7 @@ static void pnv_phb4_reset(Object *obj, ResetType type)\n pnv_phb4_err_reg_reset(phb);\n pnv_phb4_pcie_stack_reg_reset(phb);\n pnv_phb4_regb_err_reg_reset(phb);\n+ phb->regs[PHB_PCIE_CRESET >> 3] = 0xE000000000000000;\n }\n \n static void pnv_phb4_instance_init(Object *obj)\n@@ -1754,6 +1818,9 @@ static void pnv_phb4_instance_init(Object *obj)\n \n /* XIVE interrupt source object */\n object_initialize_child(obj, \"source\", &phb->xsrc, TYPE_XIVE_SOURCE);\n+\n+ /* Initialize RO-mask of registers */\n+ pnv_phb4_ro_mask_init(phb);\n }\n \n void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb)\n@@ -1933,6 +2000,7 @@ static const TypeInfo pnv_phb4_type_info = {\n .parent = TYPE_DEVICE,\n .instance_init = pnv_phb4_instance_init,\n .instance_size = sizeof(PnvPHB4),\n+ .class_size = sizeof(PnvPHB4Class),\n .class_init = pnv_phb4_class_init,\n .interfaces = (const InterfaceInfo[]) {\n { TYPE_XIVE_NOTIFIER },\ndiff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h\nindex 47a5c3edf5..bea0684724 100644\n--- a/include/hw/pci-host/pnv_phb4.h\n+++ b/include/hw/pci-host/pnv_phb4.h\n@@ -19,7 +19,7 @@\n \n \n #define TYPE_PNV_PHB4 \"pnv-phb4\"\n-OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)\n+OBJECT_DECLARE_TYPE(PnvPHB4, PnvPHB4Class, PNV_PHB4)\n \n typedef struct PnvPhb4PecStack PnvPhb4PecStack;\n \n@@ -156,6 +156,17 @@ struct PnvPHB4 {\n QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;\n };\n \n+typedef struct PnvPHB4Class {\n+ DeviceClass parent_class;\n+\n+ /*\n+ * Read-only bitmask for registers\n+ * Bit value: 1 => RO bit\n+ * 0 => RW bit\n+ */\n+ uint64_t ro_mask[PNV_PHB4_NUM_REGS];\n+} PnvPHB4Class;\n+\n void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf);\n int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);\n PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);\ndiff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h\nindex df5e86d29a..dfd0e01d1e 100644\n--- a/include/hw/pci-host/pnv_phb4_regs.h\n+++ b/include/hw/pci-host/pnv_phb4_regs.h\n@@ -180,9 +180,11 @@\n #define PHB_M64_AOMASK 0x1d0\n #define PHB_M64_UPPER_BITS 0x1f0\n #define PHB_NXLATE_PREFIX 0x1f8\n-#define PHB_DMARD_SYNC 0x200\n-#define PHB_DMARD_SYNC_START PPC_BIT(0)\n-#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1)\n+#define PHB_DMA_SYNC 0x200\n+#define PHB_DMA_SYNC_RD_START PPC_BIT(0)\n+#define PHB_DMA_SYNC_RD_COMPLETE PPC_BIT(1)\n+#define PHB_DMA_SYNC_WR_START PPC_BIT(2)\n+#define PHB_DMA_SYNC_WR_COMPLETE PPC_BIT(3)\n #define PHB_RTC_INVALIDATE 0x208\n #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)\n #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31)\n@@ -370,6 +372,7 @@\n #define P32_CAP 0x228\n #define P32_CTL 0x22C\n #define P32_STAT 0x230\n+\n /* PHB4 REGB registers */\n \n /* PBL core */\n@@ -395,8 +398,8 @@\n #define PHB_PCIE_SCR 0x1A00\n #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15)\n #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35)\n+#define PHB_PCIE_SCR_PLW_X16 PPC_BIT(41) /* x16 */\n #define PHB_PCIE_BNR 0x1A08\n-\n #define PHB_PCIE_CRESET 0x1A10\n #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0)\n #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1)\n@@ -405,7 +408,14 @@\n #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4)\n #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8)\n #define PHB_PCIE_HOTPLUG_STATUS 0x1A20\n+#define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3)\n+#define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9)\n #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10)\n+#define PHB_PCIE_HPSTAT_LINKACTIVE PPC_BIT(12)\n+#define PHB_PCIE_LMR 0x1A30\n+#define PHB_PCIE_LMR_CHANGELW PPC_BIT(0)\n+#define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1)\n+#define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8)\n \n #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40\n #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35)\n@@ -433,7 +443,7 @@\n \n #define PHB_PCIE_DLP_TRWCTL 0x1A80\n #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0)\n-\n+#define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1)\n #define PHB_PCIE_DLP_ERRLOG1 0x1AA0\n #define PHB_PCIE_DLP_ERRLOG2 0x1AA8\n #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0\ndiff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c\nindex 419f34987a..2078fab9a9 100644\n--- a/tests/qtest/pnv-phb4-test.c\n+++ b/tests/qtest/pnv-phb4-test.c\n@@ -73,7 +73,8 @@ static void phb4_sticky_rst_test(QTestState *qts)\n * Sticky reset test of PHB_PBL_ERR_STATUS.\n *\n * Write all 1's to reg PHB_PBL_ERR_INJECT.\n- * Updated value will be copied to reg PHB_PBL_ERR_STATUS.\n+ * RO-only bits will not be written and\n+ * updated value will be copied to reg PHB_PBL_ERR_STATUS.\n *\n * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET.\n * Verify the sticky bits are still set.\n@@ -81,7 +82,59 @@ static void phb4_sticky_rst_test(QTestState *qts)\n PHB4_XSCOM_WRITE(PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63));\n PHB4_XSCOM_WRITE(PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/\n val = PHB4_XSCOM_READ(PHB_PBL_ERR_STATUS);\n- g_assert_cmpuint(val, ==, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63)));\n+ g_assert_cmpuint(val, ==, 0xF00DFD8E00);\n+}\n+\n+/* Check that write-only bits/regs return 0 when read */\n+static void phb4_writeonly_read_test(QTestState *qts)\n+{\n+ uint64_t val;\n+\n+ /*\n+ * Set all bits of PHB_DMA_SYNC,\n+ * bits 0 and 2 are write-only and should be read as 0.\n+ */\n+ PHB4_XSCOM_WRITE(PHB_DMA_SYNC, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_DMA_SYNC);\n+ g_assert_cmpuint(val & PPC_BIT(0), ==, 0x0);\n+ g_assert_cmpuint(val & PPC_BIT(2), ==, 0x0);\n+\n+ /*\n+ * Set all bits of PHB_PCIE_HOTPLUG_STATUS,\n+ * bit 9 is write-only and should be read as 0.\n+ */\n+ PHB4_XSCOM_WRITE(PHB_PCIE_HOTPLUG_STATUS, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_PCIE_HOTPLUG_STATUS);\n+ g_assert_cmpuint(val & PPC_BIT(9), ==, 0x0);\n+\n+ /*\n+ * Set all bits of PHB_PCIE_LMR,\n+ * bits 0 and 1 are write-only and should be read as 0.\n+ */\n+ PHB4_XSCOM_WRITE(PHB_PCIE_LMR, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_PCIE_LMR);\n+ g_assert_cmpuint(val & PPC_BIT(0), ==, 0x0);\n+ g_assert_cmpuint(val & PPC_BIT(1), ==, 0x0);\n+\n+ /*\n+ * Set all bits of PHB_PCIE_DLP_TRWCTL,\n+ * write-only bit-1 should be read as 0.\n+ */\n+ PHB4_XSCOM_WRITE(PHB_PCIE_DLP_TRWCTL, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_PCIE_DLP_TRWCTL);\n+ g_assert_cmpuint(val & PPC_BIT(1), ==, 0x0);\n+\n+ /*\n+ * Set all bits of PHB_LEM_ERROR_AND_MASK, PHB_LEM_ERROR_OR_MASK,\n+ * both regs are write-only and should be read as 0.\n+ */\n+ PHB4_XSCOM_WRITE(PHB_LEM_ERROR_AND_MASK, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_LEM_ERROR_AND_MASK);\n+ g_assert_cmpuint(val, ==, 0x0);\n+\n+ PHB4_XSCOM_WRITE(PHB_LEM_ERROR_OR_MASK, PPC_BITMASK(0, 63));\n+ val = PHB4_XSCOM_READ(PHB_LEM_ERROR_OR_MASK);\n+ g_assert_cmpuint(val, ==, 0x0);\n }\n \n static void phb4_tests(void)\n@@ -96,6 +149,9 @@ static void phb4_tests(void)\n /* Check sticky reset of a register */\n phb4_sticky_rst_test(qts);\n \n+ /* Check write-only logic */\n+ phb4_writeonly_read_test(qts);\n+\n qtest_quit(qts);\n }\n \n", "prefixes": [ "v3", "4/9" ] }