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GET /api/patches/2195136/?format=api
{ "id": 2195136, "url": "http://patchwork.ozlabs.org/api/patches/2195136/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-6-saif.abrar@linux.vnet.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210134110.1515322-6-saif.abrar@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2026-02-10T13:40:55", "name": "[v3,5/9] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "deb6552f836b82429c3d8ab3266b064ccae252ab", "submitter": { "id": 87200, "url": "http://patchwork.ozlabs.org/api/people/87200/?format=api", "name": "Saif Abrar", "email": "saif.abrar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-6-saif.abrar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 491677, "url": "http://patchwork.ozlabs.org/api/series/491677/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491677", "date": "2026-02-10T13:40:52", "name": ": pnv/phb4: Update PHB4 to the latest PHB5 spec", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491677/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195136/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195136/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=huF7CP76;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pp1; bh=b+Z6VX\n SgIGl9rGJn9dkJWCJ7W53tYGvBFFIAymZaZ0k=; b=huF7CP76K/FiTZUHvvh4cV\n EjE/gsqbOLdOj/N9yB4DLQS9kGjWaod6ERluJQf1UAu5dYWt9MQCsDw7kuaQa6BI\n BQ+IGlk1kqXG6nzQvKHwNcXHnz6AMtrCGpE3JiGCtsgkgWuLWutExbqxCCtYuteE\n kQEC5882YdTmsWUK8T7cCbTOQ80w526aBVmzVOYr0KDYG57foJj3vyNlD8PxjoLA\n LGL2U6bbgzXjnUiZOcGQjJMT4xUlg0PacwJ6SZC0cnVBuK8WjQ5R7CJ4rcR5vboO\n nHMCfZ84pqLCwpDcw5I1aRaFGDzTS3OAZ0nXPkaDyHRHRSagQB4PqFRkzmYmpYcg\n ==", "From": "Saif Abrar <saif.abrar@linux.vnet.ibm.com>", "To": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org", "Cc": "clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com,\n marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com,\n thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com,\n saif.abrar@linux.vnet.ibm.com", "Subject": "[PATCH v3 5/9] pnv/phb4: Implement write-clear and return 1's on\n unimplemented reg read", "Date": "Tue, 10 Feb 2026 07:40:55 -0600", "Message-ID": "<20260210134110.1515322-6-saif.abrar@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "References": "<20251230102156.886288-1-saif.abrar@linux.vnet.ibm.com>\n <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-Reinject": "loops=2 maxloops=12", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEwMDExMiBTYWx0ZWRfX2RkAfTabQo9a\n be1f+JfeRL+EZAq6yiwebC33YeX2/po3wzd3WcekY0oCnRFA8dzvwoK7LiihMM24lZkEYSAeEuO\n f+dqoMR03uqGYTr5fg/vDSO91ikanCru3jgPMaScR7xE3pXz1GyOCUbEjmFv8x3l8LCEDMuF7ac\n o12YqQzjiytGjj50U7o6T4sVA0fmfyeMmCjiItjFmzGN8TJJa4Wmc0znX7Ck2El9USIrDqw6/EX\n 4bptDQla3z8rk66pG4jpPot3nub34SIoUAsjEMk4Em4TbCSVo9tr3P67Sl5VHf9KABGGEFdYBPz\n XWZUyTf+U7Pz+exShXu3ABZDmEBag+P6BLiB8AmuTrCJ3ym7533tGgkB8OrKSf8GuOBEj/9Jlvf\n Y88TZbEUxQgQ+WGWp76WovZZOyiUoorhkWliNLh87mIOG2POMlNG0V5xNzdQQ22p25eJHRzwkDX\n 95E1KlIS0aQKz3aD07g==", "X-Proofpoint-ORIG-GUID": "0XxLyN9fgRa1MALeN6tetdcHI7H1p9Rg", "X-Proofpoint-GUID": "0gM3dmshvdaeoQ27O6TkmvfilyRgGIEA", "X-Authority-Analysis": "v=2.4 cv=O+Y0fR9W c=1 sm=1 tr=0 ts=698b35b8 cx=c_pps\n a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VnNF1IyMAAAA:8\n a=aow-egSQAAAA:8 a=kBXAIK7tWc9G5WBdYtYA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=gFNbaldVC-z-bsjSTzMo:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-10_01,2026-02-10_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 priorityscore=1501 phishscore=0 adultscore=0\n malwarescore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602100112", "Received-SPF": "none client-ip=148.163.158.5;\n envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001,\n UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement write-1-to-clear and write-X-to-clear logic.\nUpdate registers with silent simple read and write.\nReturn all 1's when an unimplemented/reserved register is read.\n\nTest that reading address 0x0 returns all 1's (i.e. -1).\n\nSigned-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>\nReviewed-by: Cédric Le Goater <clg@kaod.org>\n---\nv3: Updates for coding guidelines.\n\n\n hw/pci-host/pnv_phb4.c | 190 ++++++++++++++++++++++------\n include/hw/pci-host/pnv_phb4_regs.h | 11 +-\n tests/qtest/pnv-phb4-test.c | 9 ++\n 3 files changed, 169 insertions(+), 41 deletions(-)", "diff": "diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c\nindex 07479346c2..c044e9d2a3 100644\n--- a/hw/pci-host/pnv_phb4.c\n+++ b/hw/pci-host/pnv_phb4.c\n@@ -654,8 +654,41 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n return;\n }\n \n- /* Handle masking */\n+ /* Handle RO, W1C, WxC and masking */\n switch (off) {\n+ /* W1C: Write-1-to-Clear registers */\n+ case PHB_TXE_ERR_STATUS:\n+ case PHB_RXE_ARB_ERR_STATUS:\n+ case PHB_RXE_MRG_ERR_STATUS:\n+ case PHB_RXE_TCE_ERR_STATUS:\n+ case PHB_ERR_STATUS:\n+ case PHB_REGB_ERR_STATUS:\n+ case PHB_PCIE_DLP_ERRLOG1:\n+ case PHB_PCIE_DLP_ERRLOG2:\n+ case PHB_PCIE_DLP_ERR_STATUS:\n+ case PHB_PBL_ERR_STATUS:\n+ phb->regs[off >> 3] &= ~val;\n+ return;\n+\n+ /* WxC: Clear register on any write */\n+ case PHB_PBL_ERR1_STATUS:\n+ case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR_LOG_1:\n+ case PHB_REGB_ERR1_STATUS:\n+ case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR_LOG_1:\n+ case PHB_TXE_ERR1_STATUS:\n+ case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR_LOG_1:\n+ case PHB_RXE_ARB_ERR1_STATUS:\n+ case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR_LOG_1:\n+ case PHB_RXE_MRG_ERR1_STATUS:\n+ case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR_LOG_1:\n+ case PHB_RXE_TCE_ERR1_STATUS:\n+ case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR_LOG_1:\n+ case PHB_ERR1_STATUS:\n+ case PHB_ERR_LOG_0 ... PHB_ERR_LOG_1:\n+ phb->regs[off >> 3] = 0;\n+ return;\n+\n+ /* Write value updated by masks */\n case PHB_LSI_SOURCE_ID:\n val &= PHB_LSI_SRC_ID;\n break;\n@@ -694,7 +727,6 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n case PHB_LEM_WOF:\n val = 0;\n break;\n- /* TODO: More regs ..., maybe create a table with masks... */\n \n /* Read only registers */\n case PHB_CPU_LOADSTORE_STATUS:\n@@ -703,6 +735,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n case PHB_PHB4_TCE_CAP:\n case PHB_PHB4_IRQ_CAP:\n case PHB_PHB4_EEH_CAP:\n+ case PHB_VERSION:\n+ case PHB_DMA_CHAN_STATUS:\n+ case PHB_TCE_TAG_STATUS:\n+ case PHB_PBL_BUF_STATUS:\n+ case PHB_PCIE_BNR:\n+ case PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15:\n return;\n }\n \n@@ -725,6 +763,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n pnv_phb4_update_all_msi_regions(phb);\n }\n break;\n+\n case PHB_M32_START_ADDR:\n case PHB_M64_UPPER_BITS:\n if (changed) {\n@@ -772,27 +811,63 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n break;\n \n /* Silent simple writes */\n- case PHB_ASN_CMPM:\n- case PHB_CONFIG_ADDRESS:\n- case PHB_IODA_ADDR:\n- case PHB_TCE_KILL:\n- case PHB_TCE_SPEC_CTL:\n- case PHB_PEST_BAR:\n- case PHB_PELTV_BAR:\n+ /* PHB Fundamental register set A */\n+ case PHB_CONFIG_DATA ... PHB_LOCK1:\n case PHB_RTT_BAR:\n- case PHB_LEM_FIR_ACCUM:\n- case PHB_LEM_ERROR_MASK:\n- case PHB_LEM_ACTION0:\n- case PHB_LEM_ACTION1:\n- case PHB_TCE_TAG_ENABLE:\n+ case PHB_PELTV_BAR:\n+ case PHB_PEST_BAR:\n+ case PHB_CAPI_CMPM ... PHB_M64_AOMASK:\n+ case PHB_NXLATE_PREFIX ... PHB_DMA_SYNC:\n+ case PHB_TCE_KILL ... PHB_IODA_ADDR:\n+ case PHB_PAPR_ERR_INJ_CTL ... PHB_PAPR_ERR_INJ_MASK:\n case PHB_INT_NOTIFY_ADDR:\n case PHB_INT_NOTIFY_INDEX:\n- case PHB_DMA_SYNC:\n- break;\n+ /* Fundamental register set B */\n+ case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R:\n+ /* FIR & Error registers */\n+ case PHB_LEM_FIR_ACCUM:\n+ case PHB_LEM_ERROR_MASK:\n+ case PHB_LEM_ACTION0 ... PHB_LEM_WOF:\n+ case PHB_ERR_INJECT ... PHB_ERR_AIB_FENCE_ENABLE:\n+ case PHB_ERR_STATUS_MASK ... PHB_ERR1_STATUS_MASK:\n+ case PHB_TXE_ERR_INJECT ... PHB_TXE_ERR_AIB_FENCE_ENABLE:\n+ case PHB_TXE_ERR_STATUS_MASK ... PHB_TXE_ERR1_STATUS_MASK:\n+ case PHB_RXE_ARB_ERR_INJECT ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_ARB_ERR_STATUS_MASK ... PHB_RXE_ARB_ERR1_STATUS_MASK:\n+ case PHB_RXE_MRG_ERR_INJECT ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_MRG_ERR_STATUS_MASK ... PHB_RXE_MRG_ERR1_STATUS_MASK:\n+ case PHB_RXE_TCE_ERR_INJECT ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_TCE_ERR_STATUS_MASK ... PHB_RXE_TCE_ERR1_STATUS_MASK:\n+ /* Performance monitor & Debug registers */\n+ case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1:\n+ /* REGB Registers */\n+ /* PBL core */\n+ case PHB_PBL_CONTROL:\n+ case PHB_PBL_TIMEOUT_CTRL:\n+ case PHB_PBL_NPTAG_ENABLE:\n+ case PHB_PBL_SYS_LINK_INIT:\n+ case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE:\n+ case PHB_PBL_ERR_STATUS_MASK ... PHB_PBL_ERR1_STATUS_MASK:\n+ /* PCI-E stack */\n+ case PHB_PCIE_SCR:\n+ case PHB_PCIE_DLP_STR ... PHB_PCIE_HOTPLUG_STATUS:\n+ case PHB_PCIE_LMR ... PHB_PCIE_DLP_LSR:\n+ case PHB_PCIE_DLP_RXMGN:\n+ case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_TRCRDDATA:\n+ case PHB_PCIE_DLP_ERR_COUNTERS:\n+ case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23:\n+ case PHB_PCIE_TRACE_CTRL:\n+ case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_EQ_CTL:\n+ /* Error registers */\n+ case PHB_REGB_ERR_INJECT:\n+ case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE:\n+ case PHB_REGB_ERR_STATUS_MASK ... PHB_REGB_ERR1_STATUS_MASK:\n+ break;\n \n /* Noise on anything else */\n default:\n- qemu_log_mask(LOG_UNIMP, \"phb4: reg_write 0x%\"PRIx64\"=%\"PRIx64\"\\n\",\n+ qemu_log_mask(LOG_UNIMP,\n+ \"phb4: unimplemented reg_write 0x%\"PRIx64\"=%\"PRIx64\"\\n\",\n off, val);\n }\n }\n@@ -880,36 +955,75 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size)\n return val;\n \n /* Silent simple reads */\n+ /* PHB Fundamental register set A */\n case PHB_LSI_SOURCE_ID:\n+ case PHB_DMA_CHAN_STATUS:\n case PHB_CPU_LOADSTORE_STATUS:\n- case PHB_ASN_CMPM:\n+ case PHB_CONFIG_DATA ... PHB_LOCK1:\n case PHB_PHB4_CONFIG:\n+ case PHB_RTT_BAR:\n+ case PHB_PELTV_BAR:\n case PHB_M32_START_ADDR:\n- case PHB_CONFIG_ADDRESS:\n- case PHB_IODA_ADDR:\n- case PHB_RTC_INVALIDATE:\n- case PHB_TCE_KILL:\n- case PHB_TCE_SPEC_CTL:\n case PHB_PEST_BAR:\n- case PHB_PELTV_BAR:\n- case PHB_RTT_BAR:\n+ case PHB_CAPI_CMPM:\n+ case PHB_M64_AOMASK:\n case PHB_M64_UPPER_BITS:\n- case PHB_CTRLR:\n- case PHB_LEM_FIR_ACCUM:\n- case PHB_LEM_ERROR_MASK:\n- case PHB_LEM_ACTION0:\n- case PHB_LEM_ACTION1:\n- case PHB_TCE_TAG_ENABLE:\n+ case PHB_NXLATE_PREFIX:\n+ case PHB_RTC_INVALIDATE ... PHB_IODA_ADDR:\n+ case PHB_PAPR_ERR_INJ_CTL ... PHB_ETU_ERR_SUMMARY:\n case PHB_INT_NOTIFY_ADDR:\n case PHB_INT_NOTIFY_INDEX:\n- case PHB_Q_DMA_R:\n- case PHB_ETU_ERR_SUMMARY:\n- break;\n-\n- /* Noise on anything else */\n+ /* Fundamental register set B */\n+ case PHB_CTRLR:\n+ case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R:\n+ case PHB_TCE_TAG_STATUS:\n+ /* FIR & Error registers */\n+ case PHB_LEM_FIR_ACCUM ... PHB_LEM_ERROR_MASK:\n+ case PHB_LEM_ACTION0 ... PHB_LEM_WOF:\n+ case PHB_ERR_STATUS ... PHB_ERR_AIB_FENCE_ENABLE:\n+ case PHB_ERR_LOG_0 ... PHB_ERR1_STATUS_MASK:\n+ case PHB_TXE_ERR_STATUS ... PHB_TXE_ERR_AIB_FENCE_ENABLE:\n+ case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR1_STATUS_MASK:\n+ case PHB_RXE_ARB_ERR_STATUS ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR1_STATUS_MASK:\n+ case PHB_RXE_MRG_ERR_STATUS ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR1_STATUS_MASK:\n+ case PHB_RXE_TCE_ERR_STATUS ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE:\n+ case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR1_STATUS_MASK:\n+ /* Performance monitor & Debug registers */\n+ case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1:\n+ /* REGB Registers */\n+ /* PBL core */\n+ case PHB_PBL_CONTROL:\n+ case PHB_PBL_TIMEOUT_CTRL:\n+ case PHB_PBL_NPTAG_ENABLE:\n+ case PHB_PBL_SYS_LINK_INIT:\n+ case PHB_PBL_BUF_STATUS:\n+ case PHB_PBL_ERR_STATUS ... PHB_PBL_ERR_INJECT:\n+ case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE:\n+ case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR1_STATUS_MASK:\n+ /* PCI-E stack */\n+ case PHB_PCIE_BNR ... PHB_PCIE_DLP_STR:\n+ case PHB_PCIE_DLP_LANE_PWR:\n+ case PHB_PCIE_DLP_LSR:\n+ case PHB_PCIE_DLP_RXMGN:\n+ case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_CTL:\n+ case PHB_PCIE_DLP_TRCRDDATA:\n+ case PHB_PCIE_DLP_ERRLOG1 ... PHB_PCIE_DLP_ERR_COUNTERS:\n+ case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23:\n+ case PHB_PCIE_TRACE_CTRL:\n+ case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15:\n+ /* Error registers */\n+ case PHB_REGB_ERR_STATUS ... PHB_REGB_ERR_INJECT:\n+ case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE:\n+ case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR1_STATUS_MASK:\n+ break;\n+\n+ /* Noise on unimplemented read, return all 1's */\n default:\n- qemu_log_mask(LOG_UNIMP, \"phb4: reg_read 0x%\"PRIx64\"=%\"PRIx64\"\\n\",\n- off, val);\n+ qemu_log_mask(LOG_UNIMP, \"phb4: unimplemented reg_read 0x%\"PRIx64\"\\n\",\n+ off);\n+ val = ~0ull;\n }\n return val;\n }\ndiff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h\nindex dfd0e01d1e..c1d5a83271 100644\n--- a/include/hw/pci-host/pnv_phb4_regs.h\n+++ b/include/hw/pci-host/pnv_phb4_regs.h\n@@ -407,6 +407,7 @@\n #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3)\n #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4)\n #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8)\n+#define PHB_PCIE_DLP_STR 0x1A18\n #define PHB_PCIE_HOTPLUG_STATUS 0x1A20\n #define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3)\n #define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9)\n@@ -417,6 +418,7 @@\n #define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1)\n #define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8)\n \n+#define PHB_PCIE_DLP_LANE_PWR 0x1A38\n #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40\n #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35)\n #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36, 39)\n@@ -436,18 +438,21 @@\n #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22)\n #define PHB_PCIE_DLP_TRAINING PPC_BIT(20)\n #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19)\n-\n+#define PHB_PCIE_DLP_LSR 0x1A48\n+#define PHB_PCIE_DLP_RXMGN 0x1A50\n+#define PHB_PCIE_DLP_LANEZEROCTL 0x1A70\n #define PHB_PCIE_DLP_CTL 0x1A78\n #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4)\n #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5)\n-\n #define PHB_PCIE_DLP_TRWCTL 0x1A80\n #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0)\n #define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1)\n+#define PHB_PCIE_DLP_TRCRDDATA 0x1A88\n #define PHB_PCIE_DLP_ERRLOG1 0x1AA0\n #define PHB_PCIE_DLP_ERRLOG2 0x1AA8\n #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0\n #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8\n+#define PHB_PCIE_DLP_EIC 0x1AC8\n \n #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0\n #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8\n@@ -459,6 +464,7 @@\n #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */\n #define PHB_PCIE_TRACE_CTRL 0x1B20\n #define PHB_PCIE_MISC_STRAP 0x1B30\n+#define PHB_PCIE_PHY_EQ_CTL 0x1B38\n #define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40\n #define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98\n \n@@ -592,5 +598,4 @@\n \n #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3, 63)\n \n-\n #endif /* PCI_HOST_PNV_PHB4_REGS_H */\ndiff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c\nindex 2078fab9a9..9ccb75cd5a 100644\n--- a/tests/qtest/pnv-phb4-test.c\n+++ b/tests/qtest/pnv-phb4-test.c\n@@ -137,6 +137,12 @@ static void phb4_writeonly_read_test(QTestState *qts)\n g_assert_cmpuint(val, ==, 0x0);\n }\n \n+/* Check that reading an unimplemented address 0x0 returns -1 */\n+static void phb4_unimplemented_read_test(QTestState *qts)\n+{\n+ g_assert_cmpint(PHB4_XSCOM_READ(0x0), ==, -1);\n+}\n+\n static void phb4_tests(void)\n {\n QTestState *qts = NULL;\n@@ -152,6 +158,9 @@ static void phb4_tests(void)\n /* Check write-only logic */\n phb4_writeonly_read_test(qts);\n \n+ /* Check unimplemented register read */\n+ phb4_unimplemented_read_test(qts);\n+\n qtest_quit(qts);\n }\n \n", "prefixes": [ "v3", "5/9" ] }