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GET /api/patches/2195124/?format=api
{ "id": 2195124, "url": "http://patchwork.ozlabs.org/api/patches/2195124/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-3-saif.abrar@linux.vnet.ibm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210134110.1515322-3-saif.abrar@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2026-02-10T13:40:52", "name": "[v3,2/9] pnv/phb4: Add reset logic to PHB4", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f66dfad7ad24bc82dee9a419ea42b781a15f2a10", "submitter": { "id": 87200, "url": "http://patchwork.ozlabs.org/api/people/87200/?format=api", "name": "Saif Abrar", "email": "saif.abrar@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210134110.1515322-3-saif.abrar@linux.vnet.ibm.com/mbox/", "series": [ { "id": 491677, "url": "http://patchwork.ozlabs.org/api/series/491677/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491677", "date": "2026-02-10T13:40:52", "name": ": pnv/phb4: Update PHB4 to the latest PHB5 spec", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/491677/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195124/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195124/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=PKgJ6pZJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:content-type:date:from:in-reply-to\n :message-id:mime-version:references:subject:to; s=pp1; bh=akmMNO\n UEVwqx4mxam9k0x6DfjP6Z85PwSUtX/I9nsM8=; b=PKgJ6pZJWcgadhnYtqqoGM\n rltdtPqnV+MNMNSaEwR0+fTnnXepoxEQAWRz2rMndfs1C2ifVJEGlTDbd/AqOmDI\n 5IS7wqOR4a/ntPbB5c4bNnm7rVoOZ7XuC2LJGlqcjTdT71IepWPYrJrCtpuUbLX7\n solCMIDLBxtBvrVvGb0rAYQr2urK9xWfhWly+bj3qxc0v22Yo53xxU9UZv5sIbW6\n d3nF2reS97w9vsrPAN9WRgy7AdeifjZR54G3nhN324ID+Gtg09d4VvPuRpgzHJiT\n Rl9+W2eFKP/jLhZuWTuh+An5eAQfAUxv4vJUpgR+FTCehWZF+PwT/SNbtoobDbqg\n ==", "From": "Saif Abrar <saif.abrar@linux.vnet.ibm.com>", "To": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org", "Cc": "clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com,\n marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com,\n thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com,\n saif.abrar@linux.vnet.ibm.com", "Subject": "[PATCH v3 2/9] pnv/phb4: Add reset logic to PHB4", "Date": "Tue, 10 Feb 2026 07:40:52 -0600", "Message-ID": "<20260210134110.1515322-3-saif.abrar@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "References": "<20251230102156.886288-1-saif.abrar@linux.vnet.ibm.com>\n <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-Reinject": "loops=2 maxloops=12", "X-Authority-Analysis": "v=2.4 cv=YeCwJgRf c=1 sm=1 tr=0 ts=698b3598 cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VnNF1IyMAAAA:8\n a=aow-egSQAAAA:8 a=20KFwNOVAAAA:8 a=hMFCid2_mGc3QkhTxUgA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=gFNbaldVC-z-bsjSTzMo:22", "X-Proofpoint-GUID": "Q257eMrIFBHEkV0PCSAdyFmmV6Nf5cA9", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEwMDExMiBTYWx0ZWRfX7MCi/Z3iIRwk\n 6P3RfeUYzc4QwWGdsF5T03oGXnaVhwtlnCIEqpXg4T8b4qhtpiIPv0QJxXq4SjwuAfdr52n/SWo\n HhWSgSJCvQtmxp2MdGhgROylkiJJPwQp9LihgLymhXu/dGhfqTxNbAIqxI40HEGHHRqf4lFhx9+\n skk/u35AlmuornWMrHqwG6ZhgiD3EVmI3NtfxAtzeq5uj3cbm51rlYf2M4cPqnbMDFUqUUAOdwR\n 3jSrvHwgHjo6gqIgXKq5zsbG1x5g444TV0SYUzCpZA0BwMC97QzsqfmeF2P/yRIhPz1EHkRcGS0\n hs2QI7Ne532qTii4AHi8s72R14QZMou5jEcdtnUPAzeMAatVrqhBkwdoBBruWh2R/QCozvm+ps6\n 9N1Ke9MPvFSVozK5DpM3zOZZkZv/wK9+yOkh2VrdRM9dsbu7MmtX85sK3zm6hzOJQaYNOMLadHG\n 38rK+tVew1ycNYnujPQ==", "X-Proofpoint-ORIG-GUID": "IAJMuwBpEBoy3Ss3Pj_sPbXEXHyCxQMS", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-10_01,2026-02-10_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 adultscore=0 bulkscore=0 malwarescore=0 phishscore=0\n priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602100112", "Received-SPF": "none client-ip=148.163.156.1;\n envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com", "X-Spam_score_int": "-19", "X-Spam_score": "-2.0", "X-Spam_bar": "--", "X-Spam_report": "(-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a method to be invoked on QEMU reset.\nAlso add CFG and PBL core-blocks reset logic using\nappropriate bits of PHB_PCIE_CRESET register.\n\nTested by reading the reset value of a register.\n\nSigned-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com>\nReviewed-by: Cédric Le Goater <clg@kaod.org>\nReviewed-by: Michael S. Tsirkin <mst@redhat.com>\n---\nv3: Updates for coding guidelines.\n\nv2:\n- Using the ResettableClass.\n- Reset of the root complex registers done in pnv_phb_root_port_reset_hold().\n\n hw/pci-host/pnv_phb.c | 1 +\n hw/pci-host/pnv_phb4.c | 102 +++++++++++++++++++++++++++-\n include/hw/pci-host/pnv_phb4.h | 1 +\n include/hw/pci-host/pnv_phb4_regs.h | 16 ++++-\n tests/qtest/pnv-phb4-test.c | 28 +++++++-\n 5 files changed, 144 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c\nindex 0b556d1bf5..d4f452d7b2 100644\n--- a/hw/pci-host/pnv_phb.c\n+++ b/hw/pci-host/pnv_phb.c\n@@ -232,6 +232,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type)\n pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */\n pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff);\n pci_config_set_interrupt_pin(conf, 0);\n+ pnv_phb4_cfg_core_reset(d);\n }\n \n static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)\ndiff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c\nindex 396bc47817..8334ffe42f 100644\n--- a/hw/pci-host/pnv_phb4.c\n+++ b/hw/pci-host/pnv_phb4.c\n@@ -1,7 +1,8 @@\n /*\n * QEMU PowerPC PowerNV (POWER9) PHB4 model\n+ * QEMU PowerPC PowerNV (POWER10) PHB5 model\n *\n- * Copyright (c) 2018-2020, IBM Corporation.\n+ * Copyright (c) 2018-2025, IBM Corporation.\n *\n * This code is licensed under the GPL version 2 or later. See the\n * COPYING file in the top-level directory.\n@@ -22,6 +23,7 @@\n #include \"hw/core/qdev-properties.h\"\n #include \"qom/object.h\"\n #include \"trace.h\"\n+#include \"system/reset.h\"\n \n #define phb_error(phb, fmt, ...) \\\n qemu_log_mask(LOG_GUEST_ERROR, \"phb4[%d:%d]: \" fmt \"\\n\", \\\n@@ -499,6 +501,80 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)\n }\n }\n \n+/*\n+ * Get the PCI-E capability offset from the root-port\n+ */\n+static uint32_t get_exp_offset(PCIDevice *pdev)\n+{\n+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(pdev);\n+ return rpc->exp_offset;\n+}\n+\n+void pnv_phb4_cfg_core_reset(PCIDevice *d)\n+{\n+ uint8_t *conf = d->config;\n+\n+ pci_set_word(conf + PCI_COMMAND, PCI_COMMAND_SERR);\n+ pci_set_word(conf + PCI_STATUS, PCI_STATUS_CAP_LIST);\n+ pci_set_long(conf + PCI_CLASS_REVISION, 0x06040000);\n+ pci_set_long(conf + PCI_CACHE_LINE_SIZE, BIT(16));\n+ pci_set_word(conf + PCI_MEMORY_BASE, BIT(4));\n+ pci_set_word(conf + PCI_PREF_MEMORY_BASE, BIT(0) | BIT(4));\n+ pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, PCI_PREF_RANGE_TYPE_64);\n+ pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6));\n+ pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6));\n+ pci_set_word(conf + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_SERR);\n+ pci_set_long(conf + PCI_BRIDGE_CONTROL + PCI_PM_PMC, 0xC8034801);\n+\n+ uint32_t exp_offset = get_exp_offset(d);\n+ pci_set_long(conf + exp_offset, 0x420010);\n+ pci_set_long(conf + exp_offset + PCI_EXP_DEVCAP, 0x8022);\n+ pci_set_long(conf + exp_offset + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG\n+ | PCI_EXP_DEVCTL_PAYLOAD_512B);\n+ pci_set_long(conf + exp_offset + PCI_EXP_LNKCAP, PCI_EXP_LNKCAP_LBNC\n+ | PCI_EXP_LNKCAP_DLLLARC | BIT(8) | PCI_EXP_LNKCAP_SLS_32_0GB);\n+ pci_set_word(conf + exp_offset + PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RCB);\n+ pci_set_word(conf + exp_offset + PCI_EXP_LNKSTA,\n+ (PCI_EXP_LNKSTA_NLW_X8 << 2) | PCI_EXP_LNKSTA_CLS_2_5GB);\n+ pci_set_long(conf + exp_offset + PCI_EXP_SLTCTL,\n+ PCI_EXP_SLTCTL_ASPL_DISABLE);\n+ pci_set_long(conf + exp_offset + PCI_EXP_DEVCAP2, BIT(16)\n+ | PCI_EXP_DEVCAP2_ARI | PCI_EXP_DEVCAP2_COMP_TMOUT_DIS | 0xF);\n+ pci_set_long(conf + exp_offset + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI);\n+ pci_set_long(conf + exp_offset + PCI_EXP_LNKCAP2, BIT(23)\n+ | PCI_EXP_LNKCAP2_SLS_32_0GB\n+ | PCI_EXP_LNKCAP2_SLS_16_0GB | PCI_EXP_LNKCAP2_SLS_8_0GB\n+ | PCI_EXP_LNKCAP2_SLS_5_0GB | PCI_EXP_LNKCAP2_SLS_2_5GB);\n+ pci_set_long(conf + PHB_AER_ECAP, PCI_EXT_CAP(0x1, 0x1, 0x148));\n+ pci_set_long(conf + PHB_SEC_ECAP, (0x1A0 << 20) | BIT(16)\n+ | PCI_EXT_CAP_ID_SECPCI);\n+ pci_set_long(conf + PHB_LMR_ECAP, 0x1E810027);\n+ /* LMR - Margining Lane Control / Status Register # 2 to 16 */\n+ for (int i = PHB_LMR_CTLSTA_2 ; i <= PHB_LMR_CTLSTA_16 ; i += 4) {\n+ pci_set_long(conf + i, 0x9C38);\n+ }\n+\n+ pci_set_long(conf + PHB_DLF_ECAP, 0x1F410025);\n+ pci_set_long(conf + PHB_DLF_CAP, 0x80000001);\n+ pci_set_long(conf + P16_ECAP, 0x22410026);\n+ pci_set_long(conf + P32_ECAP, 0x1002A);\n+ pci_set_long(conf + P32_CAP, 0x103);\n+}\n+\n+static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb)\n+{\n+ /* Zero all registers initially */\n+ for (int i = PHB_PBL_CONTROL ; i <= PHB_PBL_ERR1_STATUS_MASK ; i += 8) {\n+ phb->regs[i >> 3] = 0x0;\n+ }\n+\n+ /* Set specific register values */\n+ phb->regs[PHB_PBL_CONTROL >> 3] = 0xC009000000000000;\n+ phb->regs[PHB_PBL_TIMEOUT_CTRL >> 3] = 0x2020000000000000;\n+ phb->regs[PHB_PBL_NPTAG_ENABLE >> 3] = 0xFFFFFFFF00000000;\n+ phb->regs[PHB_PBL_SYS_LINK_INIT >> 3] = 0x80088B4642473000;\n+}\n+\n static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n unsigned size)\n {\n@@ -612,6 +688,18 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val,\n pnv_phb4_update_xsrc(phb);\n break;\n \n+ /* Reset core blocks */\n+ case PHB_PCIE_CRESET:\n+ if (val & PHB_PCIE_CRESET_CFG_CORE) {\n+ PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base);\n+\n+ pnv_phb4_cfg_core_reset(pci_find_device(pci->bus, 0, 0));\n+ }\n+ if (val & PHB_PCIE_CRESET_PBL) {\n+ pnv_phb4_pbl_core_reset(phb);\n+ }\n+ break;\n+\n /* Silent simple writes */\n case PHB_ASN_CMPM:\n case PHB_CONFIG_ADDRESS:\n@@ -1532,6 +1620,13 @@ static PCIIOMMUOps pnv_phb4_iommu_ops = {\n .get_address_space = pnv_phb4_dma_iommu,\n };\n \n+static void pnv_phb4_reset(Object *obj, ResetType type)\n+{\n+ PnvPHB4 *phb = PNV_PHB4(obj);\n+\n+ pnv_phb4_pbl_core_reset(phb);\n+}\n+\n static void pnv_phb4_instance_init(Object *obj)\n {\n PnvPHB4 *phb = PNV_PHB4(obj);\n@@ -1608,6 +1703,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)\n phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);\n \n pnv_phb4_xscom_realize(phb);\n+\n+ qemu_register_resettable(OBJECT(dev));\n }\n \n /*\n@@ -1701,12 +1798,15 @@ static void pnv_phb4_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n \n dc->realize = pnv_phb4_realize;\n device_class_set_props(dc, pnv_phb4_properties);\n dc->user_creatable = false;\n \n xfc->notify = pnv_phb4_xive_notify;\n+\n+ rc->phases.enter = pnv_phb4_reset;\n }\n \n static const TypeInfo pnv_phb4_type_info = {\ndiff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h\nindex de996e718b..47a5c3edf5 100644\n--- a/include/hw/pci-host/pnv_phb4.h\n+++ b/include/hw/pci-host/pnv_phb4.h\n@@ -160,6 +160,7 @@ void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf);\n int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);\n PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);\n void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);\n+void pnv_phb4_cfg_core_reset(PCIDevice *d);\n extern const MemoryRegionOps pnv_phb4_xscom_ops;\n \n /*\ndiff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h\nindex bea96f4d91..6892e21cc9 100644\n--- a/include/hw/pci-host/pnv_phb4_regs.h\n+++ b/include/hw/pci-host/pnv_phb4_regs.h\n@@ -343,6 +343,18 @@\n #define PHB_RC_CONFIG_BASE 0x1000\n #define PHB_RC_CONFIG_SIZE 0x800\n \n+#define PHB_AER_ECAP 0x100\n+#define PHB_AER_CAPCTRL 0x118\n+#define PHB_SEC_ECAP 0x148\n+#define PHB_LMR_ECAP 0x1A0\n+#define PHB_LMR_CTLSTA_2 0x1AC\n+#define PHB_LMR_CTLSTA_16 0x1E4\n+#define PHB_DLF_ECAP 0x1E8\n+#define PHB_DLF_CAP 0x1EC\n+#define P16_ECAP 0x1F4\n+#define P32_ECAP 0x224\n+#define P32_CAP 0x228\n+\n /* PHB4 REGB registers */\n \n /* PBL core */\n@@ -368,7 +380,7 @@\n #define PHB_PCIE_SCR 0x1A00\n #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15)\n #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35)\n-\n+#define PHB_PCIE_BNR 0x1A08\n \n #define PHB_PCIE_CRESET 0x1A10\n #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0)\n@@ -423,6 +435,8 @@\n #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */\n #define PHB_PCIE_TRACE_CTRL 0x1B20\n #define PHB_PCIE_MISC_STRAP 0x1B30\n+#define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40\n+#define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98\n \n /* Error */\n #define PHB_REGB_ERR_STATUS 0x1C00\ndiff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c\nindex 797f6b6c87..8cd6c1bc59 100644\n--- a/tests/qtest/pnv-phb4-test.c\n+++ b/tests/qtest/pnv-phb4-test.c\n@@ -35,6 +35,29 @@ static uint64_t pnv_phb_xscom_read(QTestState *qts, const PnvChip *chip,\n return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_data));\n }\n \n+#define PHB4_XSCOM_READ(a) pnv_phb_xscom_read(qts, \\\n+ &pnv_chips[PNV_P10_CHIP_INDEX], PHB4_XSCOM, \\\n+ PHB_SCOM_HV_IND_ADDR, PHB_SCOM_HV_IND_DATA, \\\n+ PPC_BIT(0) | (a))\n+\n+/* Assert that 'PHB PBL Control' register has correct reset value */\n+static void phb4_reset_test(QTestState *qts)\n+{\n+ g_assert_cmpuint(PHB4_XSCOM_READ(PHB_PBL_CONTROL), ==, 0xC009000000000000);\n+}\n+\n+static void phb4_tests(void)\n+{\n+ QTestState *qts = NULL;\n+\n+ qts = qtest_initf(\"-machine powernv10 -accel tcg\");\n+\n+ /* Check reset value of a register */\n+ phb4_reset_test(qts);\n+\n+ qtest_quit(qts);\n+}\n+\n /* Assert that 'PHB - Version Register' bits[24:31] are as expected */\n static void phb_version_test(const void *data)\n {\n@@ -72,8 +95,6 @@ static void phb_version_test(const void *data)\n /* PHB Version register bits [24:31] */\n ver = ver >> (63 - 31);\n g_assert_cmpuint(ver, ==, expected_ver);\n-\n- qtest_quit(qts);\n }\n \n /* Verify versions of all supported PHB's */\n@@ -94,5 +115,8 @@ int main(int argc, char **argv)\n /* PHB[345] tests */\n add_phbX_version_test();\n \n+ /* PHB4 specific tests */\n+ qtest_add_func(\"phb4\", phb4_tests);\n+\n return g_test_run();\n }\n", "prefixes": [ "v3", "2/9" ] }