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GET /api/patches/2195121/?format=api
{ "id": 2195121, "url": "http://patchwork.ozlabs.org/api/patches/2195121/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20260210133843.1078463-3-tmaimon77@gmail.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210133843.1078463-3-tmaimon77@gmail.com>", "list_archive_url": null, "date": "2026-02-10T13:38:43", "name": "[v1,2/2] watchdog: npcm: Add reset status support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e76adf208d2b54190b35e9e278b2bd1cc8447dc2", "submitter": { "id": 72291, "url": "http://patchwork.ozlabs.org/api/people/72291/?format=api", "name": "Tomer Maimon", "email": "tmaimon77@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20260210133843.1078463-3-tmaimon77@gmail.com/mbox/", "series": [ { "id": 491674, "url": "http://patchwork.ozlabs.org/api/series/491674/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=491674", "date": "2026-02-10T13:38:41", "name": "watchdog: npcm: Add reset status detection support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491674/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195121/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195121/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <openbmc+bounces-1348-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=h6fMtwce;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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Implement GCR register integration via syscon for\nreset status detection and configurable reset type mapping via device\ntree properties.\n\nSigned-off-by: Tomer Maimon <tmaimon77@gmail.com>\n---\n drivers/watchdog/npcm_wdt.c | 110 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 110 insertions(+)", "diff": "diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c\nindex e62ea054bc61..ebece5d6240a 100644\n--- a/drivers/watchdog/npcm_wdt.c\n+++ b/drivers/watchdog/npcm_wdt.c\n@@ -12,9 +12,25 @@\n #include <linux/platform_device.h>\n #include <linux/slab.h>\n #include <linux/watchdog.h>\n+#include <linux/regmap.h>\n+#include <linux/mfd/syscon.h>\n+\n+#define NPCM7XX_RESSR_OFFSET\t0x6C\n+#define NPCM7XX_INTCR2_OFFSET\t0x60\n \n #define NPCM_WTCR\t0x1C\n \n+#define NPCM7XX_PORST\tBIT(31)\n+#define NPCM7XX_CORST\tBIT(30)\n+#define NPCM7XX_WD0RST\tBIT(29)\n+#define NPCM7XX_WD1RST\tBIT(24)\n+#define NPCM7XX_WD2RST\tBIT(23)\n+#define NPCM7XX_SWR1RST\tBIT(28)\n+#define NPCM7XX_SWR2RST\tBIT(27)\n+#define NPCM7XX_SWR3RST\tBIT(26)\n+#define NPCM7XX_SWR4RST\tBIT(25)\n+#define NPCM8XX_RST\t(GENMASK(31, 23) | GENMASK(15, 12))\n+\n #define NPCM_WTCLK\t(BIT(10) | BIT(11))\t/* Clock divider */\n #define NPCM_WTE\tBIT(7)\t\t\t/* Enable */\n #define NPCM_WTIE\tBIT(6)\t\t\t/* Enable irq */\n@@ -45,6 +61,9 @@ struct npcm_wdt {\n \tstruct watchdog_device wdd;\n \tvoid __iomem\t\t*reg;\n \tstruct clk\t\t*clk;\n+\tu32\t\t\tcard_reset;\n+\tu32\t\t\text1_reset;\n+\tu32\t\t\text2_reset;\n };\n \n static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)\n@@ -185,6 +204,95 @@ static const struct watchdog_ops npcm_wdt_ops = {\n \t.restart = npcm_wdt_restart,\n };\n \n+static u32 npcm_wdt_reset_type(const char *reset_type)\n+{\n+\tif (!strcmp(reset_type, \"porst\"))\n+\t\treturn NPCM7XX_PORST;\n+\telse if (!strcmp(reset_type, \"corst\"))\n+\t\treturn NPCM7XX_CORST;\n+\telse if (!strcmp(reset_type, \"wd0\"))\n+\t\treturn NPCM7XX_WD0RST;\n+\telse if (!strcmp(reset_type, \"wd1\"))\n+\t\treturn NPCM7XX_WD1RST;\n+\telse if (!strcmp(reset_type, \"wd2\"))\n+\t\treturn NPCM7XX_WD2RST;\n+\telse if (!strcmp(reset_type, \"sw1\"))\n+\t\treturn NPCM7XX_SWR1RST;\n+\telse if (!strcmp(reset_type, \"sw2\"))\n+\t\treturn NPCM7XX_SWR2RST;\n+\telse if (!strcmp(reset_type, \"sw3\"))\n+\t\treturn NPCM7XX_SWR3RST;\n+\telse if (!strcmp(reset_type, \"sw4\"))\n+\t\treturn NPCM7XX_SWR4RST;\n+\n+\treturn 0;\n+}\n+\n+static void npcm_get_reset_status(struct npcm_wdt *wdt, struct device *dev)\n+{\n+\tconst char *card_reset_type;\n+\tconst char *ext1_reset_type;\n+\tconst char *ext2_reset_type;\n+\tstruct regmap *gcr_regmap;\n+\tu32 rstval, ressrval;\n+\tint ret;\n+\n+\tgcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, \"syscon\");\n+\tif (IS_ERR(gcr_regmap)) {\n+\t\tdev_warn(dev, \"Failed to find gcr syscon, WD reset status not supported\\n\");\n+\t\treturn;\n+\t}\n+\n+\tret = of_property_read_string(dev->of_node,\n+\t\t\t\t \"nuvoton,card-reset-type\",\n+\t\t\t\t &card_reset_type);\n+\tif (ret)\n+\t\twdt->card_reset = NPCM7XX_PORST;\n+\telse\n+\t\twdt->card_reset = npcm_wdt_reset_type(card_reset_type);\n+\n+\tret = of_property_read_string(dev->of_node,\n+\t\t\t\t \"nuvoton,ext1-reset-type\",\n+\t\t\t\t &ext1_reset_type);\n+\tif (ret)\n+\t\twdt->ext1_reset = 0;\n+\telse\n+\t\twdt->ext1_reset = npcm_wdt_reset_type(ext1_reset_type);\n+\n+\tret = of_property_read_string(dev->of_node,\n+\t\t\t\t \"nuvoton,ext2-reset-type\",\n+\t\t\t\t &ext2_reset_type);\n+\tif (ret)\n+\t\twdt->ext2_reset = 0;\n+\telse\n+\t\twdt->ext2_reset = npcm_wdt_reset_type(ext2_reset_type);\n+\n+\tregmap_read(gcr_regmap, NPCM7XX_INTCR2_OFFSET, &rstval);\n+\t/* prefer the most specific SoC first */\n+\tif (of_device_is_compatible(dev->of_node, \"nuvoton,npcm845-wdt\")) {\n+\t\tregmap_write(gcr_regmap, NPCM7XX_INTCR2_OFFSET,\n+\t\t\t rstval & ~NPCM8XX_RST);\n+\t} else if (of_device_is_compatible(dev->of_node, \"nuvoton,npcm750-wdt\")) {\n+\t\tif ((rstval & NPCM7XX_PORST) == 0) {\n+\t\t\trstval = NPCM7XX_PORST;\n+\t\t\tregmap_write(gcr_regmap, NPCM7XX_INTCR2_OFFSET,\n+\t\t\t\t rstval | NPCM7XX_PORST);\n+\t\t} else {\n+\t\t\trstval = 0;\n+\t\t}\n+\t\tregmap_read(gcr_regmap, NPCM7XX_RESSR_OFFSET, &ressrval);\n+\t\trstval |= ressrval;\n+\t\tregmap_write(gcr_regmap, NPCM7XX_RESSR_OFFSET, ressrval);\n+\t}\n+\n+\tif (rstval & wdt->card_reset)\n+\t\twdt->wdd.bootstatus |= WDIOF_CARDRESET;\n+\tif (rstval & wdt->ext1_reset)\n+\t\twdt->wdd.bootstatus |= WDIOF_EXTERN1;\n+\tif (rstval & wdt->ext2_reset)\n+\t\twdt->wdd.bootstatus |= WDIOF_EXTERN2;\n+}\n+\n static int npcm_wdt_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -208,6 +316,8 @@ static int npcm_wdt_probe(struct platform_device *pdev)\n \tif (irq < 0)\n \t\treturn irq;\n \n+\tnpcm_get_reset_status(wdt, dev);\n+\n \twdt->wdd.info = &npcm_wdt_info;\n \twdt->wdd.ops = &npcm_wdt_ops;\n \twdt->wdd.min_timeout = 1;\n", "prefixes": [ "v1", "2/2" ] }