Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2195105/?format=api
{ "id": 2195105, "url": "http://patchwork.ozlabs.org/api/patches/2195105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260210090029.728636-6-brian.ruley@gehealthcare.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210090029.728636-6-brian.ruley@gehealthcare.com>", "list_archive_url": null, "date": "2026-02-10T09:00:27", "name": "[v2,5/6] video: imx: ipuv3: move clock code to legacy", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6746bff6a2938e755cb2d173a4a716ac3730ec40", "submitter": { "id": 89422, "url": "http://patchwork.ozlabs.org/api/people/89422/?format=api", "name": "Brian Ruley", "email": "brian.ruley@gehealthcare.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260210090029.728636-6-brian.ruley@gehealthcare.com/mbox/", "series": [ { "id": 491668, "url": "http://patchwork.ozlabs.org/api/series/491668/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491668", "date": "2026-02-10T09:00:24", "name": "Enable the IPUv3 driver to use CCF", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491668/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195105/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.a=rsa-sha256 header.s=selector1 header.b=rcALdKO6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=gehealthcare.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gehealthcare.com header.i=@gehealthcare.com\n header.b=\"rcALdKO6\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=gehealthcare.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=Brian.Ruley@gehealthcare.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9Lnz6fbqz1xwH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 23:43:19 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 94E3783DEB;\n\tTue, 10 Feb 2026 13:42:03 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 4534D83CEA; Tue, 10 Feb 2026 10:01:01 +0100 (CET)", "from DM5PR21CU001.outbound.protection.outlook.com\n (mail-centralusazlp170110009.outbound.protection.outlook.com\n [IPv6:2a01:111:f403:c111::9])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id AA84883CB5\n for <u-boot@lists.denx.de>; Tue, 10 Feb 2026 10:00:57 +0100 (CET)", "from BYAPR06CA0061.namprd06.prod.outlook.com (2603:10b6:a03:14b::38)\n by BY1PR22MB5533.namprd22.prod.outlook.com (2603:10b6:a03:4ab::18)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.17; Tue, 10 Feb\n 2026 09:00:51 +0000", "from SJ5PEPF000001EA.namprd05.prod.outlook.com\n (2603:10b6:a03:14b:cafe::42) by BYAPR06CA0061.outlook.office365.com\n (2603:10b6:a03:14b::38) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9611.8 via Frontend Transport; Tue,\n 10 Feb 2026 09:00:51 +0000", "from atlrelay2.compute.ge-healthcare.net (165.85.157.49) by\n SJ5PEPF000001EA.mail.protection.outlook.com (10.167.242.198) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9611.8 via Frontend Transport; Tue, 10 Feb 2026 09:00:51 +0000", "from zoo11.fihel.lab.ge-healthcare.net\n (zoo11.fihel.lab.ge-healthcare.net [10.168.174.93])\n by builder1.fihel.lab.ge-healthcare.net (Postfix) with ESMTP id 04E73FB3EB;\n Tue, 10 Feb 2026 11:00:48 +0200 (EET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,T_SPF_PERMERROR autolearn=no\n autolearn_force=no version=3.4.2", "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=u9jCDJu6XA5wylR1e0kJdQK0ApP/bnI+Fp1uVNqblFo8+ktySPrno+RwBbS/Qq+lql3kmWHKWuxoVzi4gDbKKvNkLMWDiAjyoFWkqhSnSAOQGgUh32FnN3XDIjzP2wCyzTTuToAxP0pCQm0fAt8zQSJSNFQip/VtbgCQQP0Oq6mzRAe/PdP04NHzwyW/TxJWBrQerYibzf2PyyhemGoRtVS0L+ULdp0qJ0z+T4OVTcOdOyAY/z2gxNosXOHdcgdG5vrA3Td6gXcvioMBlXeySupIVp1kFZDo6xGuwQ/x+OQM/jTNkWYF0RJMwkxQlwHBBJt0jwoEDbkXIRNiPL+Okg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=yDSPZYTuXPv1fmM+cZMk2uZfD+0AW3sq7BaObPrbU9s=;\n b=eEK64qGTTBg1FgxQO2/sisH/FzYQotVmzjJKNR9XPLewuP8HPoz+BNmbfOWjdn4jmVOw53zinVc4ToMkdDS6fmYfe+xsHyYjVnyn22bAOXRexIwkxfrlO3TWcoCbXGg+ekwj+2AKla5PnFWLa1dkCqvEvKQIzcKltA40AgSIgENIbxzexqiQzLomV/OPlSrRZ6F0Tt6ZIoZEPCCx5qK3SBYo+37QAQaxYduoxxvgl0+euu/OGOozHBZ+rPjW9Tz5qpeGOnADW3uu2P+dEnhTJKaA4F3lRS/49zov0gV72gBdF4rxAISV7aMDp383+P8au6dX6VSebYcrbF1aGGgB1g==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=fail (sender ip is\n 165.85.157.49) smtp.rcpttodomain=lists.denx.de\n smtp.mailfrom=gehealthcare.com; dmarc=fail (p=quarantine sp=quarantine\n pct=100) action=quarantine header.from=gehealthcare.com; dkim=none (message\n not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gehealthcare.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=yDSPZYTuXPv1fmM+cZMk2uZfD+0AW3sq7BaObPrbU9s=;\n b=rcALdKO6To4nHKuN5iIbuvn0WMvyHtnp2syWSiMvyY6FCYRGbN0fXsosVJ52F3joGvXSQZdrpZWYYpfVomwxQ/0y/sXRgji7DJYcx/nh39F77P6kf6wXyzlCO6ABTu05cQf/ocOotA557oYiSXIOKUaNqMoBi7ytaiFPn1osuMv+Kje58SEPVuqrcQVT3vZVWATrK/d3HNY/zDfVl6S+h3vntoCfWY/1FZaAgTfjI3VFNBRKxlP2sdcu4WtAPrWgZHY2sI+CNda3MMYpZPbY3j7459M9SsfVEbEJxfEw7wVPUD/msbio38SSzGeOjteRZCBl8WrZK4wyfU+Oa4wipA==", "X-MS-Exchange-Authentication-Results": "spf=fail (sender IP is 165.85.157.49)\n smtp.mailfrom=gehealthcare.com; dkim=none (message not signed)\n header.d=none;dmarc=fail action=quarantine header.from=gehealthcare.com;", "Received-SPF": "Fail (protection.outlook.com: domain of gehealthcare.com does\n not designate 165.85.157.49 as permitted sender)\n receiver=protection.outlook.com; client-ip=165.85.157.49;\n helo=atlrelay2.compute.ge-healthcare.net;", "From": "Brian Ruley <brian.ruley@gehealthcare.com>", "To": "u-boot@lists.denx.de, Tom Rini <trini@konsulko.com>,\n Anatolij Gustschin <ag.dev.uboot@gmail.com>", "Cc": "Brian Ruley <brian.ruley@gehealthcare.com>,\n Alexander Graf <agraf@csgraf.de>,\n Alper Nebi Yasak <alpernebiyasak@gmail.com>,\n Miquel Raynal <miquel.raynal@bootlin.com>, Simon Glass <sjg@chromium.org>,\n Stefano Babic <sbabic@nabladev.com>", "Subject": "[PATCH v2 5/6] video: imx: ipuv3: move clock code to legacy", "Date": "Tue, 10 Feb 2026 11:00:27 +0200", "Message-Id": "<20260210090029.728636-6-brian.ruley@gehealthcare.com>", "X-Mailer": "git-send-email 2.39.5", "In-Reply-To": "<20260210090029.728636-1-brian.ruley@gehealthcare.com>", "References": "<\"20260205141332.2515996-6-brian.ruley@gehealthcare.com\">\n <20260210090029.728636-1-brian.ruley@gehealthcare.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF000001EA:EE_|BY1PR22MB5533:EE_", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "b00ff568-bb31-4abf-a017-08de6882e41d", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|36860700013|82310400026|1800799024;", "X-Microsoft-Antispam-Message-Info": "\n muFcwd4LhNgW/6F5cUsMA0nuOh9iU7EcSQlopzSw26Yw4qPlkwCMGzCuctsok4ekSL6T12lqC5Lgk+xnQmkxwAtbn4oa88ii3JjW9oLp1hkno8KwzvvY0cPO+YcZaQae4QHU7V7H/aF++rK9/8tI9vN4sXOLdxR7gZs7I40Gghe0usJfezpNHqiB81/RyH2D6ealley/zdcpxdBREnzgH7IbxzpbA47uceTVfLsZvYDtdQGwIHFOprGOWmcmquDWBLmtEqYqQUv1ojIYfVRVOY8txL4xmBzTIp/VnHC8nMmNwcxB09nrOD6zCmLXMfrOv1nMJpi3ydOuSGFF9Qe97rAGKvNACcYu9QSbI3hlzbsmE+Gc4eefdn99CgNzrfB1CY4YGYux3rbCLn4bZSTfrcJpwTY6Mf1uAS2IreqYEdgdPehHBaQM+F03jAFS7TkKD8wTYdLXkWmfWmlskylmWkBhdOh6pZ31XwZ68agR2NHsYU0dm4sELQrnoNW9SHOeS641ltxWU6vEYR3ZRiuItt2NwVEpH1S/xWSrRUtH7+He1vCWOQgKj41gWLsDcUUMXupmBzTzDTNzXQAjDVzW6ZJv0y+fA2lSi85Izst8u1w+pI6sNsnkWeZXWOvXoNt7uv0qiu3Nmsts/xkc6VkAd+iRUzLZeEeLn1d1OWGtZPYk70RvAegljGARTvltQBL3SdvkFNQxOu4INVSE+NaRkchuyrueTcVF4qMbrsfxEEZTr1RncPwXtRZCKXOZUDOcVkZi+A6PNfh0ci4Zbp9O1yh1A/5967wFVtBTpASkNlY+vCQVby/n+F9iO3tZZPFAqVTaaqSQuqFyhGQ7ytMZuXcFYQc1pcCQkvCKyl8OS4q/aRTrk7UcdHwV7nhyIP4HtxKC3/VVDsMJqqET94xWbuSs+L3fj8n4xAWL9Jli0sPq+ua2KPlPU6UY+KIxriiUKoV6wSDfL0oeCfLiA6aVHjTqe63AnMCxGk0SQJf30jJ/e4WvQjCxlnh0NPLHigV9GWkeqAuuiZY18yb7To8yc6nvabxtJFUO9HHL71IbJo+YWMSKTY2lfDIo2ieH6D/JO91s2BpYZdgET3CmIHYIGq+4fhAHe6t4vvTepJEidR9MxZ1kgvLbx0mqHWM6yQhr8vVwu3po5iZ5jE3GMnkkguWrXHxntrLogIkOTQET/gJjw4BGEatvc/fNzR83TjXiJcyHvV8NIYgIiPne4Gk7bKNcI2qaMcSLur5RMvTSVwIvA69J1aKB4ejfRpMmApR+j10beqgGf92WeXanTngn+lhkN7gF8jYXso78JnQN66dvImjxfDYw2aSy2fFm7oeq4N15QaavYU/WYFLsJ0rGRLfBEO0vqUQFfhCNfdsCbgQIKkN0/nFIP5Xio8xsnWGkpUnFi8IcDZ7Sc1UvhOWDY15aBiXat9tTCg1FkOl30iaCw9PdvPq5RaocrJeDoMsFZzitebEk0J9SnNPAn5tWuJXaPrFAaxp5ZN2/WDPtOhK7pU6j61daox7es7m/d14hBbJ2N1X2CFuPnuiok7kYypzmCCbsrhDsvdHKvqKMoUGAaO8HDb3zCw5cszLJwpzGfFJu85pbgAPo6w8bLWWlBfrRAAUq0FXibR4URGjUkxsEj4ncpl+ntOmjatQLHCWW9qgbwa8vqcm3SkqYzCJM2w==", "X-Forefront-Antispam-Report": "CIP:165.85.157.49; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:atlrelay2.compute.ge-healthcare.net;\n PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT;\n SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n CbbwPpO+KWth75iSatHbajl37zxqL9z+5kSptGfNB3I9K9Ykg1C8e17oWTqC5tggz5zc02g005XSq5EWPHoHO4U19oB6hL/V9H+Cr1cIBeL4V4qW6SegQNsmSzyqL1hdUwtkk1+MbfBWIh90hF7Bm2tf3ATmoI3lAryVOyuh9HopGa5KaOtfeRhySi7vfWWhVp6F4ejE1FSCCP+K1InbMa0fiQ6OBLeodZg/AY/ik2HxnZK9XnhLR4NJko22YM/mfXnAhcXv+j8Z9buiySVfXgW61dAfobyeUvhZBVTSbKejksONCRHmn/HDxq7tnVzMwMFCcqgb6iFT28X4Yc3/T8M/4u8ArLNPao9uf8ukebi5phv3+IJc4ZmWx4TEjQDsqC+np9BzzMlgdBlxaQ8XuRjGwA2CrftZklUGuNkTwLKP9VzsjNFStYF3Binifyo8", "X-OriginatorOrg": "gehealthcare.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Feb 2026 09:00:51.3270 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b00ff568-bb31-4abf-a017-08de6882e41d", "X-MS-Exchange-CrossTenant-Id": "9a309606-d6ec-4188-a28a-298812b4bbbf", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=9a309606-d6ec-4188-a28a-298812b4bbbf; Ip=[165.85.157.49];\n Helo=[atlrelay2.compute.ge-healthcare.net]", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "\n TreatMessagesAsInternal-SJ5PEPF000001EA.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY1PR22MB5533", "X-Mailman-Approved-At": "Tue, 10 Feb 2026 13:41:53 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "In preparation for CCF migration for IPUv3 separate existing clock code\nto legacy files. These will be used by i.MX5 that currently does not\nsupport the CCF. No functional change.\n\nSigned-off-by: Brian Ruley <brian.ruley@gehealthcare.com>\n---\n\n(no changes since v1)\n\n drivers/video/imx/Kconfig | 7 +\n drivers/video/imx/Makefile | 1 +\n drivers/video/imx/ipu.h | 60 +++++-\n drivers/video/imx/ipu_clk_legacy.c | 310 +++++++++++++++++++++++++++\n drivers/video/imx/ipu_common.c | 322 +----------------------------\n 5 files changed, 376 insertions(+), 324 deletions(-)\n create mode 100644 drivers/video/imx/ipu_clk_legacy.c", "diff": "diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig\nindex b35ba965efc..c25f209629e 100644\n--- a/drivers/video/imx/Kconfig\n+++ b/drivers/video/imx/Kconfig\n@@ -15,6 +15,13 @@ config IMX_HDMI\n \tbool \"Enable HDMI support in IPUv3\"\n \tdepends on VIDEO_IPUV3\n \n+config IPU_CLK_LEGACY\n+\tbool \"Use legacy clock management for IPU\"\n+\tdepends on VIDEO_IPUV3 && !CLK\n+\tdefault y\n+\thelp\n+\t Use legacy clock management instead of Common Clock Framework.\n+\n config IMX_LDB\n \tbool \"Freescale i.MX8MP LDB bridge\"\n \tdepends on VIDEO_BRIDGE\ndiff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile\nindex 1edf5a6bdf0..0e7f71a9f93 100644\n--- a/drivers/video/imx/Makefile\n+++ b/drivers/video/imx/Makefile\n@@ -4,5 +4,6 @@\n # Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n \n obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o\n+obj-$(CONFIG_IPU_CLK_LEGACY) += ipu_clk_legacy.o\n obj-$(CONFIG_IMX_LDB) += ldb.o\n obj-$(CONFIG_IMX_LCDIF) += lcdif.o\ndiff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h\nindex 62827dc480d..ae40e20bc28 100644\n--- a/drivers/video/imx/ipu.h\n+++ b/drivers/video/imx/ipu.h\n@@ -18,14 +18,23 @@\n #ifndef __ASM_ARCH_IPU_H__\n #define __ASM_ARCH_IPU_H__\n \n+#if !CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n+#include <clk.h>\n+#endif\n #include <ipu_pixfmt.h>\n #include <linux/types.h>\n \n+#define IPUV3_CLK_MX51 133000000\n+#define IPUV3_CLK_MX53 200000000\n+#define IPUV3_CLK_MX6Q 264000000\n+#define IPUV3_CLK_MX6DL 198000000\n+\n #define IDMA_CHAN_INVALID 0xFF\n #define HIGH_RESOLUTION_WIDTH 1024\n \n struct ipu_ctx;\n-struct ipu_di_config;\n+\n+#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY)\n \n struct clk {\n \tconst char *name;\n@@ -75,6 +84,46 @@ struct clk {\n \tint (*set_parent)(struct clk *clk, struct clk *parent);\n };\n \n+/* Legacy clock API functions */\n+void clk_enable(struct clk *clk);\n+void clk_disable(struct clk *clk);\n+int clk_get_usecount(struct clk *clk);\n+u32 clk_get_rate(struct clk *clk);\n+struct clk *clk_get_parent(struct clk *clk);\n+int clk_set_rate(struct clk *clk, unsigned long rate);\n+long clk_round_rate(struct clk *clk, unsigned long rate);\n+int clk_set_parent(struct clk *clk, struct clk *parent);\n+\n+/* IPU clock initialization */\n+int ipu_clk_init_legacy(struct ipu_ctx *ctx);\n+int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx);\n+int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id);\n+\n+#else\n+\n+static inline int clk_get_usecount(struct clk *clk)\n+{\n+ return clk->enable_count;\n+}\n+\n+/* Stub functions for non-legacy builds */\n+static inline int ipu_clk_init_legacy(struct ipu_ctx *ctx)\n+{\n+\treturn -ENOSYS;\n+}\n+\n+static inline int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx)\n+{\n+\treturn -ENOSYS;\n+}\n+\n+static inline int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id)\n+{\n+\treturn -ENOSYS;\n+}\n+\n+#endif /* CONFIG_IS_ENABLED(IPU_CLK_LEGACY) */\n+\n struct udevice;\n \n /*\n@@ -298,15 +347,6 @@ int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,\n \n u32 bytes_per_pixel(u32 fmt);\n \n-void clk_enable(struct clk *clk);\n-void clk_disable(struct clk *clk);\n-u32 clk_get_rate(struct clk *clk);\n-int clk_set_rate(struct clk *clk, unsigned long rate);\n-long clk_round_rate(struct clk *clk, unsigned long rate);\n-int clk_set_parent(struct clk *clk, struct clk *parent);\n-int clk_get_usecount(struct clk *clk);\n-struct clk *clk_get_parent(struct clk *clk);\n-\n void ipu_dump_registers(void);\n struct ipu_ctx *ipu_probe(struct udevice *dev);\n bool ipu_clk_enabled(struct ipu_ctx *ctx);\ndiff --git a/drivers/video/imx/ipu_clk_legacy.c b/drivers/video/imx/ipu_clk_legacy.c\nnew file mode 100644\nindex 00000000000..8aaafa2a080\n--- /dev/null\n+++ b/drivers/video/imx/ipu_clk_legacy.c\n@@ -0,0 +1,310 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Legacy IPU clock management for i.MX5/6 without Common Clock Framework\n+ *\n+ * (C) Copyright 2026\n+ * Brian Ruley, GE HealthCare, brian.ruley@gehealthcare.com\n+ */\n+\n+#include \"ipu.h\"\n+#include \"ipu_regs.h\"\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/io.h>\n+#include <div64.h>\n+#include <dm/devres.h>\n+#include <linux/err.h>\n+#include <log.h>\n+\n+extern struct mxc_ccm_reg *mxc_ccm;\n+\n+void clk_enable(struct clk *clk)\n+{\n+\tif (clk) {\n+\t\tif (clk->usecount++ == 0)\n+\t\t\tclk->enable(clk);\n+\t}\n+}\n+\n+void clk_disable(struct clk *clk)\n+{\n+\tif (clk) {\n+\t\tif (!(--clk->usecount)) {\n+\t\t\tif (clk->disable)\n+\t\t\t\tclk->disable(clk);\n+\t\t}\n+\t}\n+}\n+\n+int clk_get_usecount(struct clk *clk)\n+{\n+\tif (clk == NULL)\n+\t\treturn 0;\n+\n+\treturn clk->usecount;\n+}\n+\n+u32 clk_get_rate(struct clk *clk)\n+{\n+\tif (!clk)\n+\t\treturn 0;\n+\n+\treturn clk->rate;\n+}\n+\n+struct clk *clk_get_parent(struct clk *clk)\n+{\n+\tif (!clk)\n+\t\treturn 0;\n+\n+\treturn clk->parent;\n+}\n+\n+int clk_set_rate(struct clk *clk, unsigned long rate)\n+{\n+\tif (!clk)\n+\t\treturn 0;\n+\n+\tif (clk->set_rate)\n+\t\tclk->set_rate(clk, rate);\n+\n+\treturn clk->rate;\n+}\n+\n+long clk_round_rate(struct clk *clk, unsigned long rate)\n+{\n+\tif (clk == NULL || !clk->round_rate)\n+\t\treturn 0;\n+\n+\treturn clk->round_rate(clk, rate);\n+}\n+\n+int clk_set_parent(struct clk *clk, struct clk *parent)\n+{\n+\tclk->parent = parent;\n+\tif (clk->set_parent)\n+\t\treturn clk->set_parent(clk, parent);\n+\treturn 0;\n+}\n+\n+static int clk_ipu_enable(struct clk *clk)\n+{\n+\tu32 reg;\n+\n+\treg = __raw_readl(clk->enable_reg);\n+\treg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;\n+\t__raw_writel(reg, clk->enable_reg);\n+\n+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n+\treg = __raw_readl(&mxc_ccm->ccdr);\n+\treg &= ~MXC_CCM_CCDR_IPU_HS_MASK;\n+\t__raw_writel(reg, &mxc_ccm->ccdr);\n+\n+\treg = __raw_readl(&mxc_ccm->clpcr);\n+\treg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;\n+\t__raw_writel(reg, &mxc_ccm->clpcr);\n+#endif\n+\treturn 0;\n+}\n+\n+static void clk_ipu_disable(struct clk *clk)\n+{\n+\tu32 reg;\n+\n+\treg = __raw_readl(clk->enable_reg);\n+\treg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);\n+\t__raw_writel(reg, clk->enable_reg);\n+\n+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n+\treg = __raw_readl(&mxc_ccm->ccdr);\n+\treg |= MXC_CCM_CCDR_IPU_HS_MASK;\n+\t__raw_writel(reg, &mxc_ccm->ccdr);\n+\n+\treg = __raw_readl(&mxc_ccm->clpcr);\n+\treg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;\n+\t__raw_writel(reg, &mxc_ccm->clpcr);\n+#endif\n+}\n+\n+static void ipu_pixel_clk_recalc(struct clk *clk)\n+{\n+\tu32 div;\n+\tu64 final_rate = (unsigned long long)clk->parent->rate * 16;\n+\n+\tdiv = __raw_readl(DI_BS_CLKGEN0(clk->id));\n+\tdebug(\"read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\\n\", div,\n+\t final_rate, clk->parent->rate);\n+\n+\tclk->rate = 0;\n+\tif (div != 0) {\n+\t\tdo_div(final_rate, div);\n+\t\tclk->rate = final_rate;\n+\t}\n+}\n+\n+static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,\n+\t\t\t\t\t unsigned long rate)\n+{\n+\tu64 div, final_rate;\n+\tu32 remainder;\n+\tu64 parent_rate = (unsigned long long)clk->parent->rate * 16;\n+\n+\tdiv = parent_rate;\n+\tremainder = do_div(div, rate);\n+\tif (remainder > (rate / 2))\n+\t\tdiv++;\n+\tif (div < 0x10)\n+\t\tdiv = 0x10;\n+\tif (div & ~0xFEF)\n+\t\tdiv &= 0xFF8;\n+\telse {\n+\t\tif ((div & 0xC) == 0xC) {\n+\t\t\tdiv += 0x10;\n+\t\t\tdiv &= ~0xF;\n+\t\t}\n+\t}\n+\tfinal_rate = parent_rate;\n+\tdo_div(final_rate, div);\n+\n+\treturn final_rate;\n+}\n+\n+static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)\n+{\n+\tu64 div, parent_rate;\n+\tu32 remainder;\n+\n+\tparent_rate = (unsigned long long)clk->parent->rate * 16;\n+\tdiv = parent_rate;\n+\tremainder = do_div(div, rate);\n+\tif (remainder > (rate / 2))\n+\t\tdiv++;\n+\n+\tif ((div & 0xC) == 0xC) {\n+\t\tdiv += 0x10;\n+\t\tdiv &= ~0xF;\n+\t}\n+\tif (div > 0x1000)\n+\t\tdebug(\"Overflow, DI_BS_CLKGEN0 div:0x%x\\n\", (u32)div);\n+\n+\t__raw_writel(div, DI_BS_CLKGEN0(clk->id));\n+\t__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));\n+\n+\tdo_div(parent_rate, div);\n+\tclk->rate = parent_rate;\n+\n+\treturn 0;\n+}\n+\n+static int ipu_pixel_clk_enable(struct clk *clk)\n+{\n+\tu32 disp_gen = __raw_readl(IPU_DISP_GEN);\n+\tdisp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;\n+\t__raw_writel(disp_gen, IPU_DISP_GEN);\n+\n+\treturn 0;\n+}\n+\n+static void ipu_pixel_clk_disable(struct clk *clk)\n+{\n+\tu32 disp_gen = __raw_readl(IPU_DISP_GEN);\n+\tdisp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;\n+\t__raw_writel(disp_gen, IPU_DISP_GEN);\n+}\n+\n+static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)\n+{\n+\tu32 di_gen = __raw_readl(DI_GENERAL(clk->id));\n+\tstruct ipu_ctx *ctx = clk->ctx;\n+\n+\tif (parent == ctx->ipu_clk)\n+\t\tdi_gen &= ~DI_GEN_DI_CLK_EXT;\n+\telse if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk)\n+\t\tdi_gen |= DI_GEN_DI_CLK_EXT;\n+\telse\n+\t\treturn -EINVAL;\n+\n+\t__raw_writel(di_gen, DI_GENERAL(clk->id));\n+\tipu_pixel_clk_recalc(clk);\n+\treturn 0;\n+}\n+\n+int ipu_pixel_clk_init_legacy(struct ipu_ctx *ctx, int id)\n+{\n+\tstruct clk *pixel_clk;\n+\n+\tpixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL);\n+\tif (!pixel_clk)\n+\t\treturn -ENOMEM;\n+\n+\tpixel_clk->name = \"pixel_clk\";\n+\tpixel_clk->id = id;\n+\tpixel_clk->ctx = ctx;\n+\tpixel_clk->recalc = ipu_pixel_clk_recalc;\n+\tpixel_clk->set_rate = ipu_pixel_clk_set_rate;\n+\tpixel_clk->round_rate = ipu_pixel_clk_round_rate;\n+\tpixel_clk->set_parent = ipu_pixel_clk_set_parent;\n+\tpixel_clk->enable = ipu_pixel_clk_enable;\n+\tpixel_clk->disable = ipu_pixel_clk_disable;\n+\tpixel_clk->usecount = 0;\n+\n+\tctx->pixel_clk[id] = pixel_clk;\n+\treturn 0;\n+}\n+\n+int ipu_clk_init_legacy(struct ipu_ctx *ctx)\n+{\n+\tstruct clk *ipu_clk;\n+\n+\tipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL);\n+\tif (!ipu_clk)\n+\t\treturn -ENOMEM;\n+\n+\tipu_clk->name = \"ipu_clk\";\n+\tipu_clk->ctx = ctx;\n+#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n+\tipu_clk->enable_reg =\n+\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5));\n+\tipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET;\n+#else\n+\tipu_clk->enable_reg =\n+\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3));\n+\tipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;\n+#endif\n+\n+\tipu_clk->enable = clk_ipu_enable;\n+\tipu_clk->disable = clk_ipu_disable;\n+\tipu_clk->usecount = 0;\n+\n+#if CONFIG_IS_ENABLED(MX51)\n+\tipu_clk->rate = IPUV3_CLK_MX51;\n+#elif CONFIG_IS_ENABLED(MX53)\n+\tipu_clk->rate = IPUV3_CLK_MX53;\n+#else\n+\tipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;\n+#endif\n+\n+\tctx->ipu_clk = ipu_clk;\n+\treturn 0;\n+}\n+\n+#if !defined CFG_SYS_LDB_CLOCK\n+#define CFG_SYS_LDB_CLOCK 65000000\n+#endif\n+\n+int ipu_ldb_clk_init_legacy(struct ipu_ctx *ctx)\n+{\n+\tstruct clk *ldb_clk;\n+\n+\tldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL);\n+\tif (!ldb_clk)\n+\t\treturn -ENOMEM;\n+\n+\tldb_clk->name = \"ldb_clk\";\n+\tldb_clk->ctx = ctx;\n+\tldb_clk->rate = CFG_SYS_LDB_CLOCK;\n+\tldb_clk->usecount = 0;\n+\n+\tctx->ldb_clk = ldb_clk;\n+\treturn 0;\n+}\ndiff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c\nindex e9897ee79d2..d994053394f 100644\n--- a/drivers/video/imx/ipu_common.c\n+++ b/drivers/video/imx/ipu_common.c\n@@ -31,8 +31,8 @@\n #include <linux/types.h>\n #include <log.h>\n \n-extern struct mxc_ccm_reg *mxc_ccm;\n-extern u32 *ipu_cpmem_base;\n+u32 *ipu_cpmem_base;\n+u32 *ipu_dc_tmpl_reg;\n \n struct ipu_ch_param_word {\n \tu32 data[5];\n@@ -92,126 +92,6 @@ struct ipu_ch_param {\n \n #define IPU_SW_RST_TOUT_USEC (10000)\n \n-#define IPUV3_CLK_MX51 133000000\n-#define IPUV3_CLK_MX53 200000000\n-#define IPUV3_CLK_MX6Q 264000000\n-#define IPUV3_CLK_MX6DL 198000000\n-\n-void clk_enable(struct clk *clk)\n-{\n-\tif (clk) {\n-\t\tif (clk->usecount++ == 0)\n-\t\t\tclk->enable(clk);\n-\t}\n-}\n-\n-void clk_disable(struct clk *clk)\n-{\n-\tif (clk) {\n-\t\tif (!(--clk->usecount)) {\n-\t\t\tif (clk->disable)\n-\t\t\t\tclk->disable(clk);\n-\t\t}\n-\t}\n-}\n-\n-int clk_get_usecount(struct clk *clk)\n-{\n-\tif (clk == NULL)\n-\t\treturn 0;\n-\n-\treturn clk->usecount;\n-}\n-\n-u32 clk_get_rate(struct clk *clk)\n-{\n-\tif (!clk)\n-\t\treturn 0;\n-\n-\treturn clk->rate;\n-}\n-\n-struct clk *clk_get_parent(struct clk *clk)\n-{\n-\tif (!clk)\n-\t\treturn 0;\n-\n-\treturn clk->parent;\n-}\n-\n-int clk_set_rate(struct clk *clk, unsigned long rate)\n-{\n-\tif (!clk)\n-\t\treturn 0;\n-\n-\tif (clk->set_rate)\n-\t\tclk->set_rate(clk, rate);\n-\n-\treturn clk->rate;\n-}\n-\n-long clk_round_rate(struct clk *clk, unsigned long rate)\n-{\n-\tif (clk == NULL || !clk->round_rate)\n-\t\treturn 0;\n-\n-\treturn clk->round_rate(clk, rate);\n-}\n-\n-int clk_set_parent(struct clk *clk, struct clk *parent)\n-{\n-\tclk->parent = parent;\n-\tif (clk->set_parent)\n-\t\treturn clk->set_parent(clk, parent);\n-\treturn 0;\n-}\n-\n-static int clk_ipu_enable(struct clk *clk)\n-{\n-\tu32 reg;\n-\n-\treg = __raw_readl(clk->enable_reg);\n-\treg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;\n-\t__raw_writel(reg, clk->enable_reg);\n-\n-#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n-\t/* Handshake with IPU when certain clock rates are changed. */\n-\treg = __raw_readl(&mxc_ccm->ccdr);\n-\treg &= ~MXC_CCM_CCDR_IPU_HS_MASK;\n-\t__raw_writel(reg, &mxc_ccm->ccdr);\n-\n-\t/* Handshake with IPU when LPM is entered as its enabled. */\n-\treg = __raw_readl(&mxc_ccm->clpcr);\n-\treg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;\n-\t__raw_writel(reg, &mxc_ccm->clpcr);\n-#endif\n-\treturn 0;\n-}\n-\n-static void clk_ipu_disable(struct clk *clk)\n-{\n-\tu32 reg;\n-\n-\treg = __raw_readl(clk->enable_reg);\n-\treg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);\n-\t__raw_writel(reg, clk->enable_reg);\n-\n-#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n-\t/*\n-\t * No handshake with IPU whe dividers are changed\n-\t * as its not enabled.\n-\t */\n-\treg = __raw_readl(&mxc_ccm->ccdr);\n-\treg |= MXC_CCM_CCDR_IPU_HS_MASK;\n-\t__raw_writel(reg, &mxc_ccm->ccdr);\n-\n-\t/* No handshake with IPU when LPM is entered as its not enabled. */\n-\treg = __raw_readl(&mxc_ccm->clpcr);\n-\treg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;\n-\t__raw_writel(reg, &mxc_ccm->clpcr);\n-#endif\n-}\n-\n /*\n * Function to initialize the ipu clock\n *\n@@ -221,43 +101,8 @@ static void clk_ipu_disable(struct clk *clk)\n */\n static int ipu_clk_init(struct ipu_ctx *ctx)\n {\n-\tstruct clk *ipu_clk;\n-\n-\tipu_clk = devm_kzalloc(ctx->dev, sizeof(*ipu_clk), GFP_KERNEL);\n-\tif (!ipu_clk)\n-\t\treturn -ENOMEM;\n-\n-\tipu_clk->name = \"ipu_clk\";\n-\tipu_clk->ctx = ctx;\n-#if CONFIG_IS_ENABLED(MX51) || CONFIG_IS_ENABLED(MX53)\n-\tipu_clk->enable_reg =\n-\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5));\n-\tipu_clk->enable_shift = MXC_CCM_CCGR5_IPU_OFFSET;\n-#else\n-\tipu_clk->enable_reg =\n-\t\t(u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR3));\n-\tipu_clk->enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;\n-#endif\n-\n-\tipu_clk->enable = clk_ipu_enable;\n-\tipu_clk->disable = clk_ipu_disable;\n-\tipu_clk->usecount = 0;\n-\n-#if CONFIG_IS_ENABLED(MX51)\n-\tipu_clk->rate = IPUV3_CLK_MX51;\n-#elif CONFIG_IS_ENABLED(MX53)\n-\tipu_clk->rate = IPUV3_CLK_MX53;\n-#else\n-\tipu_clk->rate = is_mx6sdl() ? IPUV3_CLK_MX6DL : IPUV3_CLK_MX6Q;\n-#endif\n-\n-\tctx->ipu_clk = ipu_clk;\n-\treturn 0;\n-};\n-\n-#if !defined CFG_SYS_LDB_CLOCK\n-#define CFG_SYS_LDB_CLOCK 65000000\n-#endif\n+\treturn ipu_clk_init_legacy(ctx);\n+}\n \n /*\n * Function to initialize the ldb dummy clock\n@@ -268,23 +113,8 @@ static int ipu_clk_init(struct ipu_ctx *ctx)\n */\n static int ipu_ldb_clk_init(struct ipu_ctx *ctx)\n {\n-\tstruct clk *ldb_clk;\n-\n-\tldb_clk = devm_kzalloc(ctx->dev, sizeof(*ldb_clk), GFP_KERNEL);\n-\tif (!ldb_clk)\n-\t\treturn -ENOMEM;\n-\n-\tldb_clk->name = \"ldb_clk\";\n-\tldb_clk->ctx = ctx;\n-\tldb_clk->rate = CFG_SYS_LDB_CLOCK;\n-\tldb_clk->usecount = 0;\n-\n-\tctx->ldb_clk = ldb_clk;\n-\treturn 0;\n-};\n-\n-u32 *ipu_cpmem_base;\n-u32 *ipu_dc_tmpl_reg;\n+\treturn ipu_ldb_clk_init_legacy(ctx);\n+}\n \n /* Static functions */\n \n@@ -320,124 +150,6 @@ static inline void ipu_ch_param_set_buffer(u32 ch, int buf_num,\n #define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)\n #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))\n \n-static void ipu_pixel_clk_recalc(struct clk *clk)\n-{\n-\tu32 div;\n-\tu64 final_rate = (unsigned long long)clk->parent->rate * 16;\n-\n-\tdiv = __raw_readl(DI_BS_CLKGEN0(clk->id));\n-\tdebug(\"read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\\n\", div,\n-\t final_rate, clk->parent->rate);\n-\n-\tclk->rate = 0;\n-\tif (div != 0) {\n-\t\tdo_div(final_rate, div);\n-\t\tclk->rate = final_rate;\n-\t}\n-}\n-\n-static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,\n-\t\t\t\t\t unsigned long rate)\n-{\n-\tu64 div, final_rate;\n-\tu32 remainder;\n-\tu64 parent_rate = (unsigned long long)clk->parent->rate * 16;\n-\n-\t/*\n-\t * Calculate divider\n-\t * Fractional part is 4 bits,\n-\t * so simply multiply by 2^4 to get fractional part.\n-\t */\n-\tdiv = parent_rate;\n-\tremainder = do_div(div, rate);\n-\t/* Round the divider value */\n-\tif (remainder > (rate / 2))\n-\t\tdiv++;\n-\tif (div < 0x10) /* Min DI disp clock divider is 1 */\n-\t\tdiv = 0x10;\n-\tif (div & ~0xFEF)\n-\t\tdiv &= 0xFF8;\n-\telse {\n-\t\t/* Round up divider if it gets us closer to desired pix clk */\n-\t\tif ((div & 0xC) == 0xC) {\n-\t\t\tdiv += 0x10;\n-\t\t\tdiv &= ~0xF;\n-\t\t}\n-\t}\n-\tfinal_rate = parent_rate;\n-\tdo_div(final_rate, div);\n-\n-\treturn final_rate;\n-}\n-\n-static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)\n-{\n-\tu64 div, parent_rate;\n-\tu32 remainder;\n-\n-\tparent_rate = (unsigned long long)clk->parent->rate * 16;\n-\tdiv = parent_rate;\n-\tremainder = do_div(div, rate);\n-\t/* Round the divider value */\n-\tif (remainder > (rate / 2))\n-\t\tdiv++;\n-\n-\t/* Round up divider if it gets us closer to desired pix clk */\n-\tif ((div & 0xC) == 0xC) {\n-\t\tdiv += 0x10;\n-\t\tdiv &= ~0xF;\n-\t}\n-\tif (div > 0x1000)\n-\t\tdebug(\"Overflow, DI_BS_CLKGEN0 div:0x%x\\n\", (u32)div);\n-\n-\t__raw_writel(div, DI_BS_CLKGEN0(clk->id));\n-\n-\t/*\n-\t * Setup pixel clock timing\n-\t * Down time is half of period\n-\t */\n-\t__raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));\n-\n-\tdo_div(parent_rate, div);\n-\n-\tclk->rate = parent_rate;\n-\n-\treturn 0;\n-}\n-\n-static int ipu_pixel_clk_enable(struct clk *clk)\n-{\n-\tu32 disp_gen = __raw_readl(IPU_DISP_GEN);\n-\tdisp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;\n-\t__raw_writel(disp_gen, IPU_DISP_GEN);\n-\n-\treturn 0;\n-}\n-\n-static void ipu_pixel_clk_disable(struct clk *clk)\n-{\n-\tu32 disp_gen = __raw_readl(IPU_DISP_GEN);\n-\tdisp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;\n-\t__raw_writel(disp_gen, IPU_DISP_GEN);\n-}\n-\n-static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)\n-{\n-\tu32 di_gen = __raw_readl(DI_GENERAL(clk->id));\n-\tstruct ipu_ctx *ctx = clk->ctx;\n-\n-\tif (parent == ctx->ipu_clk)\n-\t\tdi_gen &= ~DI_GEN_DI_CLK_EXT;\n-\telse if (!IS_ERR(ctx->di_clk[clk->id]) && parent == ctx->ldb_clk)\n-\t\tdi_gen |= DI_GEN_DI_CLK_EXT;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\t__raw_writel(di_gen, DI_GENERAL(clk->id));\n-\tipu_pixel_clk_recalc(clk);\n-\treturn 0;\n-}\n-\n /*\n * Function to initialize the pixel clock\n *\n@@ -447,26 +159,8 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)\n */\n static int ipu_pixel_clk_init(struct ipu_ctx *ctx, int id)\n {\n-\tstruct clk *pixel_clk;\n-\n-\tpixel_clk = devm_kzalloc(ctx->dev, sizeof(*pixel_clk), GFP_KERNEL);\n-\tif (!pixel_clk)\n-\t\treturn -ENOMEM;\n-\n-\tpixel_clk->name = \"pixel_clk\";\n-\tpixel_clk->id = id;\n-\tpixel_clk->ctx = ctx;\n-\tpixel_clk->recalc = ipu_pixel_clk_recalc;\n-\tpixel_clk->set_rate = ipu_pixel_clk_set_rate;\n-\tpixel_clk->round_rate = ipu_pixel_clk_round_rate;\n-\tpixel_clk->set_parent = ipu_pixel_clk_set_parent;\n-\tpixel_clk->enable = ipu_pixel_clk_enable;\n-\tpixel_clk->disable = ipu_pixel_clk_disable;\n-\tpixel_clk->usecount = 0;\n-\n-\tctx->pixel_clk[id] = pixel_clk;\n-\treturn 0;\n-};\n+\treturn ipu_pixel_clk_init_legacy(ctx, id);\n+}\n \n /*\n * This function resets IPU\n", "prefixes": [ "v2", "5/6" ] }