Patch Detail
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put:
Update a patch.
GET /api/patches/2195097/?format=api
{ "id": 2195097, "url": "http://patchwork.ozlabs.org/api/patches/2195097/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260210052359.2644-1-chen.huei.lok@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210052359.2644-1-chen.huei.lok@altera.com>", "list_archive_url": null, "date": "2026-02-10T05:23:59", "name": "[v1] arm: socfpga: soc64: separate reset manager into common and platform-family parts", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c39d893287a33a119330987fd4dae11f6f606478", "submitter": { "id": 92584, "url": "http://patchwork.ozlabs.org/api/people/92584/?format=api", "name": "Chen Huei Lok", "email": "chen.huei.lok@altera.com" }, "delegate": { "id": 152680, "url": "http://patchwork.ozlabs.org/api/users/152680/?format=api", "username": "TIENFONG", "first_name": "TIEN FONG", "last_name": "CHEE", "email": "tien.fong.chee@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260210052359.2644-1-chen.huei.lok@altera.com/mbox/", "series": [ { "id": 491667, "url": "http://patchwork.ozlabs.org/api/series/491667/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491667", "date": "2026-02-10T05:23:59", "name": "[v1] arm: socfpga: soc64: separate reset manager into common and platform-family parts", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491667/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195097/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195097/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=q586HbVc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com;\n dkim=pass header.d=altera.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=axxfMwK8m9vw5GE8IiMrV4Mz2WLKD5GTyUzvRGq2jCg=;\n b=q586HbVc65aU5+OZrLMyes1imv8Kj8JffFr3DxCDwPXZa3loffh+rJO/7Ja6qco4lEfNWHVbMZd2V/KFotWZHR/3nq5qnK6QobwEGjrtymZHjjwmAZhnXRRvF54DQDsZaiT0lAP/XP5rdYVH5pxMnEINP/DBQJ+7ffFkS6gAGVYBH83J7yhtCCUT5IiVXiTOA4htxIvlEKpfIS3+OT12ecJ4+PSS26iMhwAXIOUTHZPPpQIW1/DMU9pvC+OWFOje4XpDuhFI3E1ycvwQI3huohk5aJCJC2vBsGbAfqon/iTptqDU/9io6MedbxjwVpBGK2pFRqW8WToSD9bYnH8PkA==", "From": "Chen Huei Lok <chen.huei.lok@altera.com>", "To": "u-boot@lists.denx.de", "Cc": "Marek Vasut <marex@denx.de>,\n Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>, Tom Rini <trini@konsulko.com>,\n drosdi <danish.ahmad.rosdi@altera.com>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,\n Dinesh Maniyam <dinesh.maniyam@altera.com>,\n Boon Khai Ng <boon.khai.ng@altera.com>,\n Kok Kiang Hea <kok.kiang.hea@altera.com>,\n Chen Huei Lok <chen.huei.lok@altera.com>", "Subject": "[PATCH v1] arm: socfpga: soc64: separate reset manager into common\n and platform-family parts", "Date": "Tue, 10 Feb 2026 13:23:59 +0800", "Message-ID": "<20260210052359.2644-1-chen.huei.lok@altera.com>", "X-Mailer": "git-send-email 2.43.7", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR03CA0137.namprd03.prod.outlook.com\n (2603:10b6:a03:33c::22) To IA3PR03MB8021.namprd03.prod.outlook.com\n (2603:10b6:208:502::17)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "IA3PR03MB8021:EE_|SJ0PR03MB6533:EE_", "X-MS-Office365-Filtering-Correlation-Id": "fbe9e22c-cc69-4496-fc93-08de6864a830", "X-MS-Exchange-AtpMessageProperties": "SA", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;ARA:13230040|1800799024|366016|376014;", "X-Microsoft-Antispam-Message-Info": "\n kwiO23hGcyZ2BwcmFgZfVpZpRV3TJ77qfZ9ftuckRef70134No0w7Rxjuo6CMNU6jRIEnZBrScIgwwmRR3fJZJSsPDc3yLQpY4teJG+a4xWKVFSG7xj9YdoSAiUZz4euUw/JsbG5SlZn1Yo96FfSvUR3oAUrR3ZD+33QoiI+2uebO8cqjJxF3KyJGfZRDtJBERwbJHtveZPUWRxEh1A6LMopvuvLZjmAEwt4oB4dAAL2n8GrvndlgzOgZdZ87GBV7jVjY07tLug5FSOZXrw6ohhh7o8tkHiKfuy0lrCT4ceXtaTOo6g38xGJM8VA7UkHktcelSCY+2mrHM4fDwDkD5lXpLxylUFx1+Tt0dL7EJCkIDM+vtlfFa+ycUeWjhw9NHvB0jFjnnoU5N5AFZIehsvnpy+R6k1bAraVq0Ap5oBQbXX2tZc+tPYpONcbOGGWe5NX7IYRHYJ56g7eagrjljNJsPPKyHYtNeuqQ694Y+lysTDcLutq+W6cUe/73/+dMR46+m5gOm/fCz9SFsOHbEpuxuGfcHLNjsiHsWljjnBjksYLYIdY15dkuCpijHfHW/qLnmyKAqkVwCNnze79Xw6wxWrWSY/8SZ9y8vnhx7blziYglBLZhNqK/VSwxY8fOMp07uTSOmiQ5VRSL14sLMuhQ674g1RYYa8JkL31VakK/rpJQMOa7SWDYionsdjF2lV1Jto01JBjVUqAyCHGVy+dHIy6ZFdtMaCOlJvxRVAQlkkz3dW2TBfP8A0eQWKc4vspkNNMkJPtfxYQOloSCqDoYkA/LNfIJwx1v4mVhbaTpYCG/OzsM7MBFExgkh/DXx2IiOidyzAOVOgPn3vPQB9a7VDVwJDG11lAldW198sKTqVXVhTrOaD1F7k4rg9WZh8o+S8ugT6e5vWc0dVUJtY/QC+/Lv/sNkjFVUtfaXl2dfmZ9Mti2YYGyNdr3seN5M4dF27tv6mmfs4kuHxluN6+F+XtVugP3y/WyP7OO7wVzGNNx+BKXGv0SCfYXSkxoxFqFhcuLTNHyBuq5jH4SjP1qdZa1aW0Fq1sSU7wqwR5T5ZFESHUx8mxV6/cfwS4O42qswUj+QdbQgIU9mTB7CatAGH/BN/SGh9USKJkLNPhvzLNO6uUIrrZ+pADe7jDiAVlddunJ1Vo5w8H6+0CnGJq8mrP4+2EJ7v3Qm2IvCgheqHheUxtJBg81e/zpInYmn8GbqdhYufjhirQ/CMFYs33LUricqdTI0IXfa9F8i2Jcy0wnvpFWcoSYClqkVDCV9PlSbPS8o5Qj9RYj8ICvHvNhGEMpuFMlfX8YZg2ayYGydAgVn4OEgomcyrfnZTaa5gXqXvlQX8tmpo47nhgmR052b27HhBA/DE3kdfGpE4M2D/4GfDoAUF7IPbbqbFwYKJMgJuitZ+MmJSSLmBtT13tvh2ZoMYMtmyvgHnAx5FuRme3t2HYIIwFxWenrDCkNvalZ0atFbpMNX+KSBB3GDOx8m2twlIk/bzJrKu5zUc=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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No functional change intended.\n\nSigned-off-by: Chen Huei Lok <chen.huei.lok@altera.com>\n---\n arch/arm/mach-socfpga/Makefile | 15 ++-\n arch/arm/mach-socfpga/reset_manager_soc64.c | 94 +++++++++++++++++++\n ...> reset_manager_soc64_platform_families.c} | 75 +--------------\n 3 files changed, 106 insertions(+), 78 deletions(-)\n create mode 100644 arch/arm/mach-socfpga/reset_manager_soc64.c\n rename arch/arm/mach-socfpga/{reset_manager_s10.c => reset_manager_soc64_platform_families.c} (78%)", "diff": "diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\nindex 4e85bfb00d4..71587fd3caa 100644\n--- a/arch/arm/mach-socfpga/Makefile\n+++ b/arch/arm/mach-socfpga/Makefile\n@@ -34,7 +34,8 @@ obj-y\t+= lowlevel_init_soc64.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_soc64.o\n obj-y\t+= mmu-arm64_s10.o\n-obj-y\t+= reset_manager_s10.o\n+obj-y\t+= reset_manager_soc64.o\n+obj-y\t+= reset_manager_soc64_platform_families.o\n obj-y\t+= system_manager_soc64.o\n obj-y\t+= timer_s10.o\n obj-y\t+= wrap_handoff_soc64.o\n@@ -47,7 +48,8 @@ obj-y\t+= lowlevel_init_soc64.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_soc64.o\n obj-y\t+= mmu-arm64_s10.o\n-obj-y\t+= reset_manager_s10.o\n+obj-y\t+= reset_manager_soc64.o\n+obj-y\t+= reset_manager_soc64_platform_families.o\n obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)\t+= secure_vab.o\n obj-y\t+= system_manager_soc64.o\n obj-y\t+= timer_s10.o\n@@ -62,7 +64,8 @@ obj-y\t+= clock_manager_agilex5.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_soc64.o\n obj-y\t+= mmu-arm64_s10.o\n-obj-y\t+= reset_manager_s10.o\n+obj-y\t+= reset_manager_soc64.o\n+obj-y\t+= reset_manager_soc64_platform_families.o\n obj-y\t+= wrap_handoff_soc64.o\n obj-y\t+= wrap_pll_config_soc64.o\n obj-y\t+= altera-sysmgr.o\n@@ -79,7 +82,8 @@ obj-y\t+= lowlevel_init_soc64.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_soc64.o\n obj-y\t+= mmu-arm64_s10.o\n-obj-y\t+= reset_manager_s10.o\n+obj-y\t+= reset_manager_soc64.o\n+obj-y\t+= reset_manager_soc64_platform_families.o\n obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)\t+= secure_vab.o\n obj-y\t+= system_manager_soc64.o\n obj-y\t+= timer_s10.o\n@@ -95,7 +99,8 @@ obj-y\t+= lowlevel_init_soc64.o\n obj-y\t+= mailbox_s10.o\n obj-y\t+= misc_soc64.o\n obj-y\t+= mmu-arm64_s10.o\n-obj-y\t+= reset_manager_s10.o\n+obj-y\t+= reset_manager_soc64.o\n+obj-y\t+= reset_manager_soc64_platform_families.o\n obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)\t+= secure_vab.o\n obj-y\t+= system_manager_soc64.o\n obj-y\t+= timer_s10.o\ndiff --git a/arch/arm/mach-socfpga/reset_manager_soc64.c b/arch/arm/mach-socfpga/reset_manager_soc64.c\nnew file mode 100644\nindex 00000000000..71e9512af49\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/reset_manager_soc64.c\n@@ -0,0 +1,94 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>\n+ * Copyright (C) 2025 Altera Corporation <www.altera.com>\n+ *\n+ */\n+\n+#include <errno.h>\n+#include <exports.h>\n+#include <hang.h>\n+#include <asm/global_data.h>\n+#include <asm/io.h>\n+#include <asm/secure.h>\n+#include <asm/arch/reset_manager.h>\n+#include <asm/arch/smc_api.h>\n+#include <asm/arch/system_manager.h>\n+#include <asm/arch/timer.h>\n+#include <dt-bindings/reset/altr,rst-mgr-s10.h>\n+#include <linux/iopoll.h>\n+#include <linux/intel-smc.h>\n+#include <wait_bit.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/* Assert or de-assert SoCFPGA reset manager reset. */\n+void socfpga_per_reset(u32 reset, int set)\n+{\n+\tunsigned long reg;\n+\n+\tif (RSTMGR_BANK(reset) == 0)\n+\t\treg = RSTMGR_SOC64_MPUMODRST;\n+\telse if (RSTMGR_BANK(reset) == 1)\n+\t\treg = RSTMGR_SOC64_PER0MODRST;\n+\telse if (RSTMGR_BANK(reset) == 2)\n+\t\treg = RSTMGR_SOC64_PER1MODRST;\n+\telse if (RSTMGR_BANK(reset) == 3)\n+\t\treg = RSTMGR_SOC64_BRGMODRST;\n+\telse\t/* Invalid reset register, do nothing */\n+\t\treturn;\n+\n+\tif (set)\n+\t\tsetbits_le32(socfpga_get_rstmgr_addr() + reg,\n+\t\t\t 1 << RSTMGR_RESET(reset));\n+\telse\n+\t\tclrbits_le32(socfpga_get_rstmgr_addr() + reg,\n+\t\t\t 1 << RSTMGR_RESET(reset));\n+}\n+\n+/*\n+ * Assert reset on every peripheral but L4WD0.\n+ * Watchdog must be kept intact to prevent glitches\n+ * and/or hangs.\n+ */\n+void socfpga_per_reset_all(void)\n+{\n+\tconst u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));\n+\n+\t/* disable all except OCP and l4wd0. OCP disable later */\n+\twritel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),\n+\t socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);\n+\twritel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);\n+\twritel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);\n+}\n+\n+/*\n+ * Return non-zero if the CPU has been warm reset\n+ */\n+int cpu_has_been_warmreset(void)\n+{\n+\treturn readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &\n+\t\t\tRSTMGR_L4WD_MPU_WARMRESET_MASK;\n+}\n+\n+void print_reset_info(void)\n+{\n+\tbool iswd;\n+\tint n;\n+\tu32 stat = cpu_has_been_warmreset();\n+\n+\tprintf(\"Reset state: %s%s\", stat ? \"Warm \" : \"Cold\",\n+\t (stat & RSTMGR_STAT_SDMWARMRST) ? \"[from SDM] \" : \"\");\n+\n+\tstat &= ~RSTMGR_STAT_SDMWARMRST;\n+\tif (!stat) {\n+\t\tputs(\"\\n\");\n+\t\treturn;\n+\t}\n+\n+\tn = generic_ffs(stat) - 1;\n+\tiswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);\n+\tprintf(\"(Triggered by %s %d)\\n\", iswd ? \"Watchdog\" : \"MPU\",\n+\t iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :\n+\t (n - RSTMGR_STAT_MPU0RST_BITPOS));\n+}\ndiff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_soc64_platform_families.c\nsimilarity index 78%\nrename from arch/arm/mach-socfpga/reset_manager_s10.c\nrename to arch/arm/mach-socfpga/reset_manager_soc64_platform_families.c\nindex abb62a9b49f..04736b17b36 100644\n--- a/arch/arm/mach-socfpga/reset_manager_s10.c\n+++ b/arch/arm/mach-socfpga/reset_manager_soc64_platform_families.c\n@@ -6,6 +6,7 @@\n */\n \n #include <errno.h>\n+#include <exports.h>\n #include <hang.h>\n #include <asm/global_data.h>\n #include <asm/io.h>\n@@ -15,7 +16,6 @@\n #include <asm/arch/system_manager.h>\n #include <asm/arch/timer.h>\n #include <dt-bindings/reset/altr,rst-mgr-s10.h>\n-#include <exports.h>\n #include <linux/iopoll.h>\n #include <linux/intel-smc.h>\n #include <wait_bit.h>\n@@ -29,46 +29,6 @@ DECLARE_GLOBAL_DATA_PTR;\n #define F2SDRAM_SIDEBAND_FLAGOUTSET0\t0x50\n #define F2SDRAM_SIDEBAND_FLAGOUTCLR0\t0x54\n \n-/* Assert or de-assert SoCFPGA reset manager reset. */\n-void socfpga_per_reset(u32 reset, int set)\n-{\n-\tunsigned long reg;\n-\n-\tif (RSTMGR_BANK(reset) == 0)\n-\t\treg = RSTMGR_SOC64_MPUMODRST;\n-\telse if (RSTMGR_BANK(reset) == 1)\n-\t\treg = RSTMGR_SOC64_PER0MODRST;\n-\telse if (RSTMGR_BANK(reset) == 2)\n-\t\treg = RSTMGR_SOC64_PER1MODRST;\n-\telse if (RSTMGR_BANK(reset) == 3)\n-\t\treg = RSTMGR_SOC64_BRGMODRST;\n-\telse\t/* Invalid reset register, do nothing */\n-\t\treturn;\n-\n-\tif (set)\n-\t\tsetbits_le32(socfpga_get_rstmgr_addr() + reg,\n-\t\t\t 1 << RSTMGR_RESET(reset));\n-\telse\n-\t\tclrbits_le32(socfpga_get_rstmgr_addr() + reg,\n-\t\t\t 1 << RSTMGR_RESET(reset));\n-}\n-\n-/*\n- * Assert reset on every peripheral but L4WD0.\n- * Watchdog must be kept intact to prevent glitches\n- * and/or hangs.\n- */\n-void socfpga_per_reset_all(void)\n-{\n-\tconst u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));\n-\n-\t/* disable all except OCP and l4wd0. OCP disable later */\n-\twritel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),\n-\t\t socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);\n-\twritel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);\n-\twritel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);\n-}\n-\n static void socfpga_f2s_bridges_reset(int enable, unsigned int mask)\n {\n \tint ret;\n@@ -271,40 +231,9 @@ void socfpga_bridges_reset(int enable, unsigned int mask)\n \t\t\t\t ARRAY_SIZE(arg), NULL, 0);\n \t\tif (ret)\n \t\t\tprintf(\"Failed to %s the HPS bridges, check bridges availability. Status %d.\\n\",\n-\t\t\t\tenable ? \"enable\" : \"disable\", ret);\n+\t\t\t enable ? \"enable\" : \"disable\", ret);\n \t} else {\n \t\tsocfpga_s2f_bridges_reset(enable, mask);\n \t\tsocfpga_f2s_bridges_reset(enable, mask);\n \t}\n }\n-\n-/*\n- * Return non-zero if the CPU has been warm reset\n- */\n-int cpu_has_been_warmreset(void)\n-{\n-\treturn readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &\n-\t\t\tRSTMGR_L4WD_MPU_WARMRESET_MASK;\n-}\n-\n-void print_reset_info(void)\n-{\n-\tbool iswd;\n-\tint n;\n-\tu32 stat = cpu_has_been_warmreset();\n-\n-\tprintf(\"Reset state: %s%s\", stat ? \"Warm \" : \"Cold\",\n-\t (stat & RSTMGR_STAT_SDMWARMRST) ? \"[from SDM] \" : \"\");\n-\n-\tstat &= ~RSTMGR_STAT_SDMWARMRST;\n-\tif (!stat) {\n-\t\tputs(\"\\n\");\n-\t\treturn;\n-\t}\n-\n-\tn = generic_ffs(stat) - 1;\n-\tiswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);\n-\tprintf(\"(Triggered by %s %d)\\n\", iswd ? \"Watchdog\" : \"MPU\",\n-\t iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :\n-\t (n - RSTMGR_STAT_MPU0RST_BITPOS));\n-}\n", "prefixes": [ "v1" ] }