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GET /api/patches/2195024/?format=api
{ "id": 2195024, "url": "http://patchwork.ozlabs.org/api/patches/2195024/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260210113104.60335-8-chris.bazley@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113104.60335-8-chris.bazley@arm.com>", "list_archive_url": null, "date": "2026-02-10T11:31:00", "name": "[v9,07/11] AArch64/SVE: Relax the expectations of the popcnt-sve test", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3c7ab24e113abea5e51d7a99cddc4a649b238dc6", "submitter": { "id": 89471, "url": "http://patchwork.ozlabs.org/api/people/89471/?format=api", "name": "Christopher Bazley", "email": "Chris.Bazley@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260210113104.60335-8-chris.bazley@arm.com/mbox/", "series": [ { "id": 491659, "url": "http://patchwork.ozlabs.org/api/series/491659/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491659", "date": "2026-02-10T11:30:56", "name": "Extend BB SLP vectorization to use predicated tails", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/491659/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195024/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=dfGW5Hlq;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=dfGW5Hlq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Christopher Bazley <chris.bazley@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<rguenther@suse.de>, <Tamar.Christina@arm.com>,\n <rdsandiford@googlemail.com>, Christopher Bazley <chris.bazley@arm.com>", "Subject": "[PATCH v9 07/11] AArch64/SVE: Relax the expectations of the\n popcnt-sve test", "Date": "Tue, 10 Feb 2026 11:31:00 +0000", "Message-ID": "<20260210113104.60335-8-chris.bazley@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113104.60335-1-chris.bazley@arm.com>", "References": "<20260210113104.60335-1-chris.bazley@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509F8:EE_|AM7PR08MB5527:EE_|DB5PEPF00014B96:EE_|AS4PR08MB8069:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5b799ade-b860-464c-01c9-08de68982d6f", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|82310400026|1800799024|36860700013|13003099007;", "X-Microsoft-Antispam-Message-Info-Original": "\n GpjLrucbt11d7A1DNRYbC3sgTjg8sqdpclun8NJMqmADzsuZtnW/zkRxjDTEJuC6t7hXCCNQhjXLM+dWnzfLVJ3UixNewuCACavdMkh4Mgzmsbj+nFnA8ORhHhnjQlKNlgojsJKRBWvLX0fdiCtKfaxvRvm3kwwvswDj/eU9/AtkHSK7qvSlRfdjszaXAhiN/WoDgazYpjD/pP722d3vlNQaehJEUadp66mGUYcnId7ylc9nmxVOerqAPiUTUZNs6fYKgt9Hq9AN6V3nPQ/BYO/gFx0/wjDBdhGwvmVQrS5NTk0M29vTbCJcbzvD34oDfIt8C8VINLutJjemeWBQXZiRtk6xWaeP6ns7+ZJgelShaH4VxJ38dmlbatCe3ClD/lZ+/UX7sQN6OSVz9HjitrZ2T+3w+I3SYL+zK3qE0GVTsPsRSjumcz3hPPYRKN6NJ4OlWLUy2YR1xUGs+6hY1v2JF9dDDzf3mW/hqcOy4j0p+dIi/vlYWfPoEnyFy3ZGPgP2VO+NrBtdhUGpPwURzs0XIt7B233Kne6Qo6kwYRiH0L1tx7PVWz/4co5SDQwxY9e2t73TZKhVtXDFekhHsiyyM0zSkO4MTPOW1q0m9qG1iE4jkgGP7td4NkShee26hZGAGnhKJOdOygJrLGKeLXDBH8XYRXE3UIfRPycBJmwPUyUnWeL8t+bcFPBz0joEj+/pDeQhCbcA9Ln8vUzA2wPFWITwA76QpjZXrXGHtThnsWocR+Kax1Re9NUQUEbxMsheJX8U/GE+uhGTmzC2mBQSX1NWwx7t0iexe+relUjmfLGpmNel2V8/MIPs3LzJigyza8UOi9zRLN+vX5IcXzUS6guvwWfLR01J/bApdjygGOTacnN/aE2phR4ooFHMNUz8J7pOBdvbPQx7b1W7KntuAKVI01aK9mwS6zcbp65XiXB/2MwQi1wQ3Oz12iPp1U9Wz6jkOSpq95fQgaNh7rD3mKjI3a0V5eaMVsuDlm4GZFBppQYCppI06ICW2GXSUwXd0CXBCltLByEdZObA3ViTP7XGGcZSGwvz+GD1rEIIbNsVYPLZ0kDQEnU+P0wHAyT72hKbsGP9w8GUsvBuubliQgw9bEfoiKj+Ar/xStIXkDn3b6WadUd88y+76fO7crC5HFQiM1+iOQVg4SwoPGDQmnVgX8+qENRWNs0qrOSucjZuYIOVqW/H1fys04ROrsJuWGKQIhlu016lfGwZkKYfIBBDRgo7/tyTCHg/TKxaF02rOeBahe8YwFwiJxyMnqg4MGPZqBzzLYou4iAvAsHxOJ/cLkjiSuIaXBpCMC14nT8MdBjuOwzbCzBtBR5B+f3AeG45KrDXbsNeZlm0feCgNCnTC3WSRDUSYt5nkJJeZvRacqCi1o2WwsJGggcaxGxWBkNHF8sxFTfP8rHOtPqzx6GLRZGgqktQ8wI6sW89s4TwPG2MfQGd5aYBB+c0O5ylT2S3q39D2WIECwgqHf+0o5ryD6sILCet2FHtpY7LlXr9oC+vynXln1d9ZwEHmJ0gpglfQcHzoi4XPeVdb/QHv5IJxwTf5ZogR4pt2fyNwrrmcaSii1vIAj5/5I7sI+HsL5+cfd0gXewSPRHnKEVEskINFlr1xaaNQsk8UxI=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB5PEPF00014B96.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "When predicated tails are enabled for basic block SLP vectorization,\nthe assembly language generated by GCC when compiling popcnt-sve.c\nwill change. Relax the regular expressions used by this test in\npreparation.\n\nCurrently, analysis of f_v8hi succeeds with vector mode V16QI and the\nfollowing GIMPLE is produced:\n\nvector(8) short unsigned intD.19 vect__1.18D.4648;\n...\nvect__1.18_69 = MEM <vector(8) short unsigned intD.19>\n [(short unsigned intD.19 *)vectp.17_68 clique 1 base 1];\nvect_patt_60.19_70 = .POPCOUNT (vect__1.18_69);\n\nWith predicated tails, analysis instead succeeds with a variable-length\nvector mode and the following GIMPLE is produced:\n\nvector([8,8]) short unsigned intD.19 vect__1.18D.4649;\n...\nslp_mask_45 = .WHILE_ULT (0, 8, { 0, ... }); # VUSE <.MEM_25(D)>\nvect__1.18_46 = .MASK_LOAD (vectp.17_44, 16B, slp_mask_45, { 0, ... });\nvect_patt_36.19_47 = .POPCOUNT (vect__1.18_46);\n\nWhen lowered to RTL, the WHILE_ULT is replaced by\nreinterpretation of a V16QI as VNx8HI:\n\n(insn 7 4 8 2 (\n set (reg:V16QI 107) (mem:V16QI (reg/v/f:DI 103 [ b ]) [1 S16 A16])\n) \"gcc.target/aarch64/popcnt-sve.c\":33:8 discrim 1 -1 (nil))\n\n(insn 8 7 9 2 (\n set (reg:VNx8HI 106) (subreg:VNx8HI (reg:V16QI 107) 0))\n \"gcc.target/aarch64/popcnt-sve.c\":33:8 discrim 1 -1 (nil))\n\nA mask is still required to lower POPCOUNT, so an all-ones mask\nis synthesized:\n\n(insn 9 8 10 2 (set (reg:VNx16BI 108)\n (const_vector:VNx16BI repeat [(const_int 1 [0x1])\n ])) \"gcc.target/aarch64/popcnt-sve.c\":69:8 discrim 1 -1\n(nil))\n\n(insn 10 9 11 2 (set (reg:VNx4SI 105)\n (unspec:VNx4SI [\n (subreg:VNx4BI (reg:VNx16BI 108) 0)\n (popcount:VNx4SI (reg:VNx4SI 106))\n ] UNSPEC_PRED_X))\n \"gcc.target/aarch64/popcnt-sve.c\":69:8 discrim 1 -1\n(nil))\n\nHowever, this mask is not the same as the specific-width mask\ncurrently expected by the tests.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/popcnt-sve.c: Update test expectations\n\tto allow both current and alternative valid mask\n\tspecifications.\n\n---\n gcc/testsuite/gcc.target/aarch64/popcnt-sve.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)", "diff": "diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c b/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c\nindex c3b4c69b4b4..117a5ca8f1b 100644\n--- a/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c\n+++ b/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c\n@@ -4,7 +4,7 @@\n \n /*\n ** f_v4hi:\n-**\tptrue\t(p[0-7]).b, vl8\n+**\tptrue\t(p[0-7]).b, (?:vl8|all)\n **\tldr\td([0-9]+), \\[x0\\]\n **\tcnt\tz\\2.h, \\1/m, z\\2.h\n **\tstr\td\\2, \\[x1\\]\n@@ -21,7 +21,7 @@ f_v4hi (unsigned short *__restrict b, unsigned short *__restrict d)\n \n /*\n ** f_v8hi:\n-**\tptrue\t(p[0-7]).b, vl16\n+**\tptrue\t(p[0-7]).b, (?:vl16|all)\n **\tldr\tq([0-9]+), \\[x0\\]\n **\tcnt\tz\\2.h, \\1/m, z\\2.h\n **\tstr\tq\\2, \\[x1\\]\n@@ -42,7 +42,7 @@ f_v8hi (unsigned short *__restrict b, unsigned short *__restrict d)\n \n /*\n ** f_v2si:\n-**\tptrue\t(p[0-7]).b, vl8\n+**\tptrue\t(p[0-7]).b, (?:vl8|all)\n **\tldr\td([0-9]+), \\[x0\\]\n **\tcnt\tz\\2.s, \\1/m, z\\2.s\n **\tstr\td\\2, \\[x1\\]\n@@ -57,7 +57,7 @@ f_v2si (unsigned int *__restrict b, unsigned int *__restrict d)\n \n /*\n ** f_v4si:\n-**\tptrue\t(p[0-7]).b, vl16\n+**\tptrue\t(p[0-7]).b, (?:vl16|all)\n **\tldr\tq([0-9]+), \\[x0\\]\n **\tcnt\tz\\2.s, \\1/m, z\\2.s\n **\tstr\tq\\2, \\[x1\\]\n@@ -74,7 +74,7 @@ f_v4si (unsigned int *__restrict b, unsigned int *__restrict d)\n \n /*\n ** f_v2di:\n-**\tptrue\t(p[0-7]).b, vl16\n+**\tptrue\t(p[0-7]).b, (?:vl16|all)\n **\tldr\tq([0-9]+), \\[x0\\]\n **\tcnt\tz\\2.d, \\1/m, z\\2.d\n **\tstr\tq\\2, \\[x1\\]\n", "prefixes": [ "v9", "07/11" ] }