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GET /api/patches/2195023/?format=api
{ "id": 2195023, "url": "http://patchwork.ozlabs.org/api/patches/2195023/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260210113104.60335-9-chris.bazley@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113104.60335-9-chris.bazley@arm.com>", "list_archive_url": null, "date": "2026-02-10T11:31:01", "name": "[v9,08/11] AArch64/SVE: Optimize vec_init for partial SVE vector modes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a4684fa236851ae1b2d906e34f2337992e21ffeb", "submitter": { "id": 89471, "url": "http://patchwork.ozlabs.org/api/people/89471/?format=api", "name": "Christopher Bazley", "email": "Chris.Bazley@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260210113104.60335-9-chris.bazley@arm.com/mbox/", "series": [ { "id": 491659, "url": "http://patchwork.ozlabs.org/api/series/491659/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491659", "date": "2026-02-10T11:30:56", "name": "Extend BB SLP vectorization to use predicated tails", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/491659/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195023/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195023/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=SyvxYE17;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=SyvxYE17;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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dkim=pass (signature was verified)\n header.d=arm.com;dmarc=pass action=none header.from=arm.com;", "spf=pass (sender IP is 172.205.89.229)\n smtp.mailfrom=arm.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=arm.com;" ], "Received-SPF": [ "Pass (protection.outlook.com: domain of arm.com designates\n 4.158.2.129 as permitted sender) receiver=protection.outlook.com;\n client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C", "Pass (protection.outlook.com: domain of arm.com designates\n 172.205.89.229 as permitted sender) receiver=protection.outlook.com;\n client-ip=172.205.89.229; helo=nebula.arm.com; pr=C" ], "From": "Christopher Bazley <chris.bazley@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "<rguenther@suse.de>, <Tamar.Christina@arm.com>,\n <rdsandiford@googlemail.com>, Christopher Bazley <chris.bazley@arm.com>", "Subject": "[PATCH v9 08/11] AArch64/SVE: Optimize vec_init for partial SVE\n vector modes", "Date": "Tue, 10 Feb 2026 11:31:01 +0000", "Message-ID": "<20260210113104.60335-9-chris.bazley@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113104.60335-1-chris.bazley@arm.com>", "References": "<20260210113104.60335-1-chris.bazley@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n DB1PEPF000509F4:EE_|GV4PR08MB11579:EE_|DB1PEPF000509F8:EE_|AM7PR08MB5414:EE_", "X-MS-Office365-Filtering-Correlation-Id": "88f7b897-b80b-4960-144c-08de68982eb8", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|1800799024|82310400026|376014|36860700013;", "X-Microsoft-Antispam-Message-Info-Original": "\n ysxohB5Ep+T0Ddj1q3uSi+DFGBto18NWe2TfssnTxaxwARhVf1BEq66H7UIfwnwPOYHrInxkOuXlfocdLEZdmNiZ28v/I4FxrnBvt+1tQZm446vv1IGVL7M/0qdIhtyTSZtHlmkQFz9xcdbyOhuFRuB7xYwzu4Btez9edm73knXujirhYjlR4el8A5y0dqQMnsJh9jTwxDW/bkcsjAdq6/euF4/bj291fDb64pT/ZMqmYQNkszPSDkvE6BWGyUWD4PZcNMgv9+zeyYDphKlH8vl/3WNJqRBUwO5FtfXQbwpZJ/vmCc7vxyIqD+irzwAV2RyocUSP3818G13u4mPPgF75qSwcPkmepNdQg5P+pSYQgFkIm3Vw/8IfFrzxqdQWOXBlGpYpQhKleqU8GGDYndciqRz/z1w/rgfLpCIat7FXfr2My4lGj0Qh4/68wxn2wbwVheX2N8xEJfDcjBhase7uVzmsg7jm7sXYpHMQTzwLkG3fa1A/o3GyctdVccC6Ihcim6/8yASBQPlJF5SPZ7ADfFbAY2xB2/3I1uws9pP2ODO/AsqT92JaH9JXbIA1YcxOpZDVJjDRPK1CjxfFxvGm4Ca+UQCrdXaO8+J11434No4WR6bfdVymcMpETJ/mLtnm0EvV8fo8ZFMB2TwgzoI1nuqz0/5U3I3rbFkwCGa7LQ6ad1bzWPKFYCPuhS9A+099txoU6nWpyxiY82PKfsSVgBEi29d31MZLNiVB6p6D7o9zDtu4hIhPPkS+6zo1BOlvaPGWlrQHJMAG9IHjbLv/dxsgiExM/jbZ8DTLMv9RQqmEiQJsZPYUjRExpOa7r2/G1pmFl4B+F/qMYhHVt1E0Y43YgCtyBBzibOydZAyy1kyXq2kiauQFTTC4nnm/jREz62SJS7uoBmGROn48hIgOcHzSJbORPDGDVSw1Pd7BiqnPNbEl4bDskykclMMQYahJHYr55pg0/Jsoi6RPCq1wBJ3uDLg06P7EB0r75I9DwJbpVeIQuxNz+cUEnHl6Tw1AYEIxRPWLh8R4iSMxFpKd5Iriy5L1KhE86dktw+FD4egGqEDjmOXAROLhWHUT0jP6vYL8wgO12F6CroIBRMFrBTnkuqjnd6qiX96S1rEvdOXXagt0p1n6ls4+WX5yWj9u2w6ZS54xIWigd4mlMJo4UHlB6KpBYtIFWLPghfs9H8gZ5FT5vTo9JT1NS8ZmeH0JJXt5h70p+Uk2l/JBKNBuK5FhWx8RtNWbPYZH4NAxB9UOdGtx+rdjGCQEaSSWMT1MhDk8Xmcjsagj7LowTk4QUb+5hUQ3PDnJDyxOF5Kyqx1QXjEu1CGkyd+n/OfjmD0M3DvtzUtyJKCapjN7cC9lYy5e5RxEh2aqnnJj+pqQ3C/RSnuvvwKmOhju2fw8XgqYmIsY9VUP2IwRh1MUZYFU/tWkFVGAT8ToHsBJu+NgZ0oHtaz/oqcPITa5KP+O5+PdZrGju1SJ3KF3XFz/0ZOCDSHPYuj5dmPutX0tO/PtIHvm7ukY+OEGKvnInPNhMkRja12chr4bLv4IoAnhSztdu0O50lQtcJ9oEZHoLHgDsRfIYjeri2OCA0nDo6ADkbU/81s9T+NynHF2x2HXqYU2woJ5uy8x7pkqYPbIgZs=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB1PEPF000509F8.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "When basic block vectorization is extended to support predicated\nvector tails, it attempts to vectorize more stores. This is only\ndone if the cost model deems it profitable, but the cost model\nassumes that vec_init is cheap; in practice, that was not always\ntrue.\n\nFor example,\n\n uint8_t * vectp.2689;\n vector([4,4]) unsigned char _846;\n vector([4,4]) <signed-boolean:4> slp_mask_848;\n ...\n _846 = {_20, _30, _40, _50};\n vectp.2689_847 = src_61(D) + 64;\n slp_mask_848 = .WHILE_ULT (0, 4, { 0, ... });\n .MASK_STORE (vectp.2689_847, 8B, slp_mask_848, _846);\n\nwas expected to have a vector cost of 4 (the same as the scalar\ncost) but the code actually generated for\n\n_846 = {_20, _30, _40, _50};\n\nwas a repetitive series of write-modify-read operations\nusing four stack locations for temporary storage:\n\n(set (reg:VNx16BI Y)\n (const_vector:VNx16BI repeat [\n (const_int 1 [0x1])\n ]))\n\n(set (mem/c:VNx4QI (plus:DI (reg/f:DI 96 virtual-stack-vars)\n (const_poly_int:DI [-O, -O])) [0 S[O, O] A8])\n (unspec:VNx4QI [\n (subreg:VNx4BI (reg:VNx16BI Y) 0)\n (reg:VNx4QI 205 [ _845 ])\n ] UNSPEC_PRED_X))\n\n(set (reg:QI Z)\n (subreg:QI (reg:SI X [ _W ]) 0))\n\n(set (mem/c:QI (plus:DI (reg/f:DI 96 virtual-stack-vars)\n (const_poly_int:DI [-O, -O])) [0 S1 A8])\n (reg:QI Z))\n\n(set (reg:VNx4QI 205 [ _845 ])\n (unspec:VNx4QI [\n (subreg:VNx4BI (reg:VNx16BI V) 0)\n (mem/c:VNx4QI (plus:DI (reg/f:DI 96 virtual-stack-vars)\n (const_poly_int:DI [-O, -O])) [0 S[O, O] A8])\n ] UNSPEC_PRED_X))\n\n(repeated four times)\n\nwhich compiled to something like:\n\n\taddpl x5, sp, #6\n\tst1b {z27.s}, p7, sp, #3, mul vl\n\tstrb w10, [x5]\n\tld1b {z28.s}, p7/z, sp, #3, mul vl\n\n(repeated four times)\n\nWith these changes, the compiled code is instead:\n\n\tmov\tz31.b, w0\n\tinsr\tz31.s, s28\n\tinsr\tz31.s, s29\n\tinsr\tz31.s, s30\n\nwhich is not yet optimal but is a great improvement.\n\nTo achieve that, \"vec_init<mode><Vel>\" was modified to\naccept all SVE vector modes, which means that the\nassociated function aarch64_sve_expand_vector_init\nmust now handle all partial modes (namely, VNx8QI, VNx4QI,\nVNx2QI, VNx4HI, VNx2HI, VNx2SI, VNx2HF, VNx4HF, VNx2SF,\nVNx2BF, VNx4BF).\n\nI verified that the following dependencies already\nhandle partial vector modes:\n- \"@aarch64_sve_<perm_insn><mode>\" (for ZIP1)\n- \"*vec_duplicate<mode>_reg\"\n- maybe_code_for_aarch64_sve_rev\n\nI did not verify that emit_move_insn (which is a dependency\nof aarch64_sve_expand_vector_init_handle_trailing_constants)\nhandles partial vector modes, but it seems highly likely.\n\n\"vec_shl_insert_<mode>\" has been modified to accept SVE_ALL\ninstead of only SVE_FULL and operate on container instead of\nelement types.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-sve.md: Update\n\tvec_init<mode><Vel> and vec_shl_insert_<mode> to\n\taccept all SVE vector modes.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/sve/slp_stack.c: New test.\n\n---\n gcc/config/aarch64/aarch64-sve.md | 16 +++++------\n .../gcc.target/aarch64/sve/slp_stack.c | 27 +++++++++++++++++++\n 2 files changed, 35 insertions(+), 8 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/slp_stack.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md\nindex 97fd9516959..8f783afb51d 100644\n--- a/gcc/config/aarch64/aarch64-sve.md\n+++ b/gcc/config/aarch64/aarch64-sve.md\n@@ -2945,7 +2945,7 @@ (define_insn \"@aarch64_sve_ld1ro<mode>\"\n ;; -------------------------------------------------------------------------\n \n (define_expand \"vec_init<mode><Vel>\"\n- [(match_operand:SVE_FULL 0 \"register_operand\")\n+ [(match_operand:SVE_ALL 0 \"register_operand\")\n (match_operand 1 \"\")]\n \"TARGET_SVE\"\n {\n@@ -2989,17 +2989,17 @@ (define_expand \"vec_initvnx16qivnx2qi\"\n \n ;; Shift an SVE vector left and insert a scalar into element 0.\n (define_insn \"vec_shl_insert_<mode>\"\n- [(set (match_operand:SVE_FULL 0 \"register_operand\")\n-\t(unspec:SVE_FULL\n-\t [(match_operand:SVE_FULL 1 \"register_operand\")\n+ [(set (match_operand:SVE_ALL 0 \"register_operand\")\n+\t(unspec:SVE_ALL\n+\t [(match_operand:SVE_ALL 1 \"register_operand\")\n \t (match_operand:<VEL> 2 \"aarch64_reg_or_zero\")]\n \t UNSPEC_INSR))]\n \"TARGET_SVE\"\n {@ [ cons: =0 , 1 , 2 ; attrs: movprfx ]\n- [ ?w , 0 , rZ ; * ] insr\\t%0.<Vetype>, %<vwcore>2\n- [ w , 0 , w ; * ] insr\\t%0.<Vetype>, %<Vetype>2\n- [ ??&w , w , rZ ; yes ] movprfx\\t%0, %1\\;insr\\t%0.<Vetype>, %<vwcore>2\n- [ ?&w , w , w ; yes ] movprfx\\t%0, %1\\;insr\\t%0.<Vetype>, %<Vetype>2\n+ [ ?w , 0 , rZ ; * ] insr\\t%0.<Vctype>, %<vccore>2\n+ [ w , 0 , w ; * ] insr\\t%0.<Vctype>, %<Vctype>2\n+ [ ??&w , w , rZ ; yes ] movprfx\\t%0, %1\\;insr\\t%0.<Vctype>, %<vccore>2\n+ [ ?&w , w , w ; yes ] movprfx\\t%0, %1\\;insr\\t%0.<Vctype>, %<Vctype>2\n }\n [(set_attr \"sve_type\" \"sve_int_general\")]\n )\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_stack.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_stack.c\nnew file mode 100644\nindex 00000000000..76be816e0d6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_stack.c\n@@ -0,0 +1,27 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -ftree-vectorize -mcpu=neoverse-n2 --param=aarch64-autovec-preference=sve-only -msve-vector-bits=scalable\" } */\n+\n+#include <stdint.h>\n+\n+/* Without an efficient implementation of vec_init for partial SVE types, a\n+ decision to vectorize a group in the basic block vectorizer can result in\n+ code that repeatedly stores a whole vector on the stack, overwrites one\n+ element, reloads the whole vector, stores it to another location,\n+ overwrites another element, etc. This is a fairly minimal reproducer. */\n+void\n+vec_slp_pathological_stack (uint8_t *src)\n+{\n+ int lt = src[-33];\n+ int l0 = src[-1];\n+ int l1 = src[31];\n+ int t0 = src[-32];\n+ int t1 = src[-31];\n+ int t2 = src[-30];\n+ src[64] = (l1 + (2 * l0) + lt + 2) >> 2;\n+ src[65] = (lt + t0 + 1) >> 1;\n+ src[66] = (t0 + t1 + 1) >> 1;\n+ src[67] = (t1 + t2 + 1) >> 1;\n+}\n+\n+/* { dg-final { scan-assembler-not {sp} } }\n+ */\n", "prefixes": [ "v9", "08/11" ] }