Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2195017/?format=api
{ "id": 2195017, "url": "http://patchwork.ozlabs.org/api/patches/2195017/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-15-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-15-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:38", "name": "[v5,14/16] arm64: dts: renesas: r9a09g047: Add PCIe node", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "518364fb0c59fc31af9eedc69c02234d3ded0171", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-15-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195017/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195017/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47081-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-47081-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.171", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KFf5jsxz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:42 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 2003E3039F5F\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:41 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7D04E3195F9;\n\tTue, 10 Feb 2026 11:33:38 +0000 (UTC)", "from relmlie5.idc.renesas.com (relmlor1.renesas.com\n [210.160.252.171])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id D2148A59;\n\tTue, 10 Feb 2026 11:33:36 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie5.idc.renesas.com with ESMTP; 10 Feb 2026 20:33:36 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id DE3CD41A1194;\n\tTue, 10 Feb 2026 20:33:30 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723218; cv=none;\n b=RMSVebxQvFYZbutW+6RtZzahUigInin0/Au/1ls3J587sIlPrUPnOG1JwbZD8ZHc28ZychXmNc/TGFxHOpexAtelSYeFuJ3Tw3gl+qWI14vIUOfIGZEZBcvo+vCE3Ry64UXGViXzP66tfyPL/1A1zTVDVqFE11ozFXwJtU8VJ2I=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723218; c=relaxed/simple;\n\tbh=QIQd8ZDWrrJElBtxDxdrXFmJCb4PemCgJwM+FMgc190=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=Tc+5rku1JhP7YzkrB37R+7o3u3djapLg97XO2p/9iYq5xq9ctoX4nPb6jwm9qUnf23Or/MA1rOsNh8n2JWkbJqYItv/OsQwImZyoxwt0xIm3YVk7qJ4jhiiNPoe7getA1bNmIDTdIsKILnV1YtxvA/ztnLntLhjIQnTolyROmCs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.171", "X-CSE-ConnectionGUID": "9kH0EtvLR7ON/brM27+w7A==", "X-CSE-MsgGUID": "SxUcma8LSiGUMo2b0WbXyA==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 14/16] arm64: dts: renesas: r9a09g047: Add PCIe node", "Date": "Tue, 10 Feb 2026 12:30:38 +0100", "Message-ID": "<20260210113041.138430-15-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "The RZ/G3E SoC family features an x2 PCIe IP. Add the PCIe node.\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: No changes\nv4: No changes\nv3: No changes\nv2:\n - Roerder interrupts and interrupt names to match binding\n\n arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 69 ++++++++++++++++++++++\n 1 file changed, 69 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi\nindex cbb48ff5028f..2eccaa7ed1c5 100644\n--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi\n+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi\n@@ -841,6 +841,75 @@ wdt3: watchdog@13000400 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpcie: pcie@13400000 {\n+\t\t\tcompatible = \"renesas,r9a09g047-pcie\";\n+\t\t\treg = <0 0x13400000 0 0x10000>;\n+\t\t\tranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,\n+\t\t\t\t <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>;\n+\t\t\tdma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tinterrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"serr\", \"serr_cor\", \"serr_nonfatal\",\n+\t\t\t\t\t \"serr_fatal\", \"axi_err\", \"inta\",\n+\t\t\t\t\t \"intb\", \"intc\", \"intd\", \"msi\",\n+\t\t\t\t\t \"link_bandwidth\", \"pm_pme\", \"dma\",\n+\t\t\t\t\t \"pcie_evt\", \"msg\", \"all\",\n+\t\t\t\t\t \"link_equalization_request\",\n+\t\t\t\t\t \"turn_off_event\", \"pmu_poweroff\",\n+\t\t\t\t\t \"d3_event_f0\", \"d3_event_f1\",\n+\t\t\t\t\t \"cfg_pmcsr_writeclear_f0\",\n+\t\t\t\t\t \"cfg_pmcsr_writeclear_f1\";\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */\n+\t\t\t\t\t<0 0 0 2 &pcie 0 0 0 1>, /* INTB */\n+\t\t\t\t\t<0 0 0 3 &pcie 0 0 0 2>, /* INTC */\n+\t\t\t\t\t<0 0 0 4 &pcie 0 0 0 3>; /* INTD */\n+\t\t\tclocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>;\n+\t\t\tclock-names = \"aclk\", \"pmu\";\n+\t\t\tresets = <&cpg 0xb2>;\n+\t\t\treset-names = \"aresetn\";\n+\t\t\tpower-domains = <&cpg>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\trenesas,sysc = <&sys>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie_port0: pcie@0,0 {\n+\t\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\t\tranges;\n+\t\t\t\tdevice_type = \"pci\";\n+\t\t\t\tvendor-id = <0x1912>;\n+\t\t\t\tdevice-id = <0x0039>;\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t};\n+\t\t};\n+\n \t\ttsu: thermal@14002000 {\n \t\t\tcompatible = \"renesas,r9a09g047-tsu\";\n \t\t\treg = <0 0x14002000 0 0x1000>;\n", "prefixes": [ "v5", "14/16" ] }