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GET /api/patches/2195016/?format=api
{ "id": 2195016, "url": "http://patchwork.ozlabs.org/api/patches/2195016/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-14-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-14-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:37", "name": "[v5,13/16] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fc545562a50da561b17b16f64fb7f3de62b780ec", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-14-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195016/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195016/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47080-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-47080-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.171", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KFY2fMdz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:37 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 86CFA303A877\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:35 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7F73A3195E8;\n\tTue, 10 Feb 2026 11:33:32 +0000 (UTC)", "from relmlie5.idc.renesas.com (relmlor1.renesas.com\n [210.160.252.171])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8CDAC318BAF;\n\tTue, 10 Feb 2026 11:33:30 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie5.idc.renesas.com with ESMTP; 10 Feb 2026 20:33:30 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 070CF41A1194;\n\tTue, 10 Feb 2026 20:33:24 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723212; cv=none;\n b=eXjM2K2O0EVn6zJNvbFkmXm03LZgGrQA4HoVdhvYRJICorTlro2B8ebHABRw0w8z5SCgJ0Xt44TeeuWaB3zc2UqmGo6XNDyOGd9iO3C4/I1dKRjQHgRwiIvsifpQ9YGIWyAIhO17w7697pjx7D9TeK3OC5aDhDC+jBD3MPq/+iI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723212; c=relaxed/simple;\n\tbh=DSMgdRPtg6TSqtdGbc/DLpA50jTB6vLb/P/wf4ev1dk=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=hteXmtPsMTkevENc4U2y1vj3A4rVRo9TJjKnZNpar1jCcGNg0DRmxm57keY5SXIn5s0+k+UGDkP9GxXlLGGfu/Nf0uadnxkUPPG9nblC0YTlG+GxTVuCIu1QIrOQDFLnLWGyuITOBeoEoWh4MXt0ao8Py+JEN13ijqVolWME+5I=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.171", "X-CSE-ConnectionGUID": "OlIdxtJXRFGx7SP7gYcaDg==", "X-CSE-MsgGUID": "66UGISzaQe+eDVRaK3V5Lg==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 13/16] PCI: rzg3s-host: Add support for RZ/G3E PCIe\n controller", "Date": "Tue, 10 Feb 2026 12:30:37 +0100", "Message-ID": "<20260210113041.138430-14-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Add support for the PCIe controller found in RZ/G3E SoCs to the existing\nRZ/G3S PCIe host driver. The RZ/G3E PCIe controller is similar to the\nRZ/G3S's, with the following key differences:\n\n - Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)\n - Uses a different reset control mechanism via AXI registers instead\n of the Linux reset framework\n - Requires specific SYSC configuration for link state control and\n Root Complex mode selection\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5:\n - Introduce rzg3s_sysc_config() helper for sys configuration\n\nv4: No changes\nv3: No changes\nv2: Collected tag.\n\n drivers/pci/controller/pcie-rzg3s-host.c | 152 ++++++++++++++++++++---\n 1 file changed, 137 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 22858a876fd8..77313cc01c02 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -111,6 +111,16 @@\n #define RZG3S_PCI_PERM_CFG_HWINIT_EN\t\tBIT(2)\n #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN\t\tBIT(1)\n \n+/* RZ/G3E specific registers */\n+#define RZG3E_PCI_RESET\t\t\t\t0x310\n+#define RZG3E_PCI_RESET_RST_OUT_B\t\tBIT(6)\n+#define RZG3E_PCI_RESET_RST_PS_B\t\tBIT(5)\n+#define RZG3E_PCI_RESET_RST_LOAD_B\t\tBIT(4)\n+#define RZG3E_PCI_RESET_RST_CFG_B\t\tBIT(3)\n+#define RZG3E_PCI_RESET_RST_RSM_B\t\tBIT(2)\n+#define RZG3E_PCI_RESET_RST_GP_B\t\tBIT(1)\n+#define RZG3E_PCI_RESET_RST_B\t\t\tBIT(0)\n+\n #define RZG3S_PCI_MSIRE(id)\t\t\t(0x600 + (id) * 0x10)\n #define RZG3S_PCI_MSIRE_ENA\t\t\tBIT(0)\n \n@@ -183,9 +193,13 @@ struct rzg3s_sysc_function {\n /**\n * struct rzg3s_sysc_info - RZ/G3S System Controller function info\n * @rst_rsm_b: Reset RSM_B function descriptor\n+ * @l1_allow: L1 power state management function descriptor\n+ * @mode: Mode configuration function descriptor\n */\n struct rzg3s_sysc_info {\n \tstruct rzg3s_sysc_function rst_rsm_b;\n+\tstruct rzg3s_sysc_function l1_allow;\n+\tstruct rzg3s_sysc_function mode;\n };\n \n /**\n@@ -1124,6 +1138,49 @@ static int rzg3s_config_deinit(struct rzg3s_pcie_host *host)\n \t\t\t\t\t host->cfg_resets);\n }\n \n+/* RZ/G3E SoC-specific config implementations */\n+static void rzg3e_pcie_config_pre_init(struct rzg3s_pcie_host *host)\n+{\n+\t/*\n+\t * De-assert LOAD_B and CFG_B during configuration phase.\n+\t * These are part of the RZ/G3E reset register, not reset framework.\n+\t * Other reset bits remain asserted until config_post_init.\n+\t */\n+\trzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,\n+\t\t\t RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B,\n+\t\t\t RZG3E_PCI_RESET_RST_LOAD_B | RZG3E_PCI_RESET_RST_CFG_B);\n+}\n+\n+static int rzg3e_config_deinit(struct rzg3s_pcie_host *host)\n+{\n+\twritel_relaxed(0, host->axi + RZG3E_PCI_RESET);\n+\treturn 0;\n+}\n+\n+static int rzg3e_config_post_init(struct rzg3s_pcie_host *host)\n+{\n+\t/* De-assert PS_B, GP_B, RST_B */\n+\trzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,\n+\t\t\t RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |\n+\t\t\t RZG3E_PCI_RESET_RST_B,\n+\t\t\t RZG3E_PCI_RESET_RST_PS_B | RZG3E_PCI_RESET_RST_GP_B |\n+\t\t\t RZG3E_PCI_RESET_RST_B);\n+\n+\t/*\n+\t * According to the RZ/G3E HW manual (Rev.1.15, Table 6.6-130\n+\t * Initialization Procedure (RC)), hardware requires >= 500us delay\n+\t * before final reset deassert.\n+\t */\n+\tfsleep(500);\n+\n+\t/* De-assert OUT_B and RSM_B to complete reset sequence */\n+\trzg3s_pcie_update_bits(host->axi, RZG3E_PCI_RESET,\n+\t\t\t RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B,\n+\t\t\t RZG3E_PCI_RESET_RST_OUT_B | RZG3E_PCI_RESET_RST_RSM_B);\n+\n+\treturn 0;\n+}\n+\n static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)\n {\n \t/*\n@@ -1266,6 +1323,47 @@ static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host)\n \treturn ret;\n }\n \n+/**\n+ * rzg3s_sysc_config - Configure SYSC registers for PCIe\n+ * @sysc: SYSC descriptor\n+ * @mode: Mode value to set (-1 to skip)\n+ * @rsm_b: RST_RSM_B value to set (-1 to skip)\n+ * @l1_allow: L1_ALLOW value to set (-1 to skip)\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int rzg3s_sysc_config(struct rzg3s_sysc *sysc, int mode, int rsm_b,\n+\t\t\t int l1_allow)\n+{\n+\tconst struct rzg3s_sysc_info *info = sysc->info;\n+\tint ret;\n+\n+\tif (mode >= 0 && info->mode.mask) {\n+\t\tret = regmap_write(sysc->regmap, info->mode.offset,\n+\t\t\t\t field_prep(info->mode.mask, mode));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (rsm_b >= 0 && info->rst_rsm_b.mask) {\n+\t\tret = regmap_update_bits(sysc->regmap, info->rst_rsm_b.offset,\n+\t\t\t\t\t info->rst_rsm_b.mask,\n+\t\t\t\t\t field_prep(info->rst_rsm_b.mask, rsm_b));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (l1_allow >= 0 && info->l1_allow.mask) {\n+\t\tret = regmap_update_bits(sysc->regmap, info->l1_allow.offset,\n+\t\t\t\t\t info->l1_allow.mask,\n+\t\t\t\t\t field_prep(info->l1_allow.mask, l1_allow));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)\n {\n \tu32 val;\n@@ -1284,6 +1382,11 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)\n \tif (ret)\n \t\tgoto config_deinit;\n \n+\t/* Enable ASPM L1 transition for SoCs that use it */\n+\tret = rzg3s_sysc_config(host->sysc, -1, -1, 1);\n+\tif (ret)\n+\t\tgoto config_deinit;\n+\n \t/* Initialize the interrupts */\n \trzg3s_pcie_irq_init(host);\n \n@@ -1631,9 +1734,12 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \t\tgoto port_refclk_put;\n \t}\n \n-\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n-\t\t\t\t sysc->info->rst_rsm_b.mask,\n-\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 1));\n+\t/*\n+\t * Put controller in RC (Root Complex) mode for SoCs that\n+\t * support it. These can operate in either EP or RC mode.\n+\t * While at it, do also de-assert RST_RSM_B.\n+\t */\n+\tret = rzg3s_sysc_config(sysc, 1, 1, -1);\n \tif (ret)\n \t\tgoto port_refclk_put;\n \n@@ -1685,9 +1791,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \t * SYSC RST_RSM_B signal need to be asserted before turning off the\n \t * power to the PHY.\n \t */\n-\tregmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n-\t\t\t sysc->info->rst_rsm_b.mask,\n-\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n+\trzg3s_sysc_config(sysc, -1, 0, -1);\n port_refclk_put:\n \tclk_put(host->port.refclk);\n \n@@ -1718,9 +1822,7 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n \tif (ret)\n \t\tgoto config_reinit;\n \n-\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n-\t\t\t\t sysc->info->rst_rsm_b.mask,\n-\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n+\tret = rzg3s_sysc_config(sysc, -1, 0, -1);\n \tif (ret)\n \t\tgoto power_resets_restore;\n \n@@ -1745,9 +1847,7 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)\n \tstruct rzg3s_sysc *sysc = host->sysc;\n \tint ret;\n \n-\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n-\t\t\t\t sysc->info->rst_rsm_b.mask,\n-\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 1));\n+\tret = rzg3s_sysc_config(sysc, 1, 1, -1);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1776,9 +1876,7 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)\n \treset_control_bulk_assert(data->num_power_resets,\n \t\t\t\t host->power_resets);\n assert_rst_rsm_b:\n-\tregmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n-\t\t\t sysc->info->rst_rsm_b.mask,\n-\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n+\trzg3s_sysc_config(sysc, -1, 0, -1);\n \treturn ret;\n }\n \n@@ -1811,11 +1909,35 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {\n \t},\n };\n \n+static const char * const rzg3e_soc_power_resets[] = { \"aresetn\" };\n+\n+static const struct rzg3s_pcie_soc_data rzg3e_soc_data = {\n+\t.power_resets = rzg3e_soc_power_resets,\n+\t.num_power_resets = ARRAY_SIZE(rzg3e_soc_power_resets),\n+\t.config_pre_init = rzg3e_pcie_config_pre_init,\n+\t.config_post_init = rzg3e_config_post_init,\n+\t.config_deinit = rzg3e_config_deinit,\n+\t.sysc_info = {\n+\t\t.l1_allow = {\n+\t\t\t.offset = 0x1020,\n+\t\t\t.mask = BIT(0),\n+\t\t},\n+\t\t.mode = {\n+\t\t\t.offset = 0x1024,\n+\t\t\t.mask = BIT(0),\n+\t\t},\n+\t},\n+};\n+\n static const struct of_device_id rzg3s_pcie_of_match[] = {\n \t{\n \t\t.compatible = \"renesas,r9a08g045-pcie\",\n \t\t.data = &rzg3s_soc_data,\n \t},\n+\t{\n+\t\t.compatible = \"renesas,r9a09g047-pcie\",\n+\t\t.data = &rzg3e_soc_data,\n+\t},\n \t{}\n };\n \n", "prefixes": [ "v5", "13/16" ] }