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GET /api/patches/2195015/?format=api
{ "id": 2195015, "url": "http://patchwork.ozlabs.org/api/patches/2195015/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-13-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-13-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:36", "name": "[v5,12/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "87882cc0b4093ada281de9754c3c153ccd81be96", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-13-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195015/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195015/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47079-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-47079-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.171", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KFR641Vz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:31 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id C1E9F300BC7A\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:29 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id F088B318BAF;\n\tTue, 10 Feb 2026 11:33:26 +0000 (UTC)", "from relmlie5.idc.renesas.com (relmlor1.renesas.com\n [210.160.252.171])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 4DEAC188713;\n\tTue, 10 Feb 2026 11:33:24 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie5.idc.renesas.com with ESMTP; 10 Feb 2026 20:33:24 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 6776C41A1194;\n\tTue, 10 Feb 2026 20:33:18 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723206; cv=none;\n b=KVUsqzCXh8VfPyidu89vfT1omeLhEsUiX1ccIgYJ5u0iJzsLcFYQRUkFH53Hl7WBoAck8loYgXe2OcqYnCfI+jcU3RNKWm7judy+UdC4xN3fJmRch2sPb29H/TN04ji3oLFsyH9dIOn6oOZWA0SwICwCKswp/+WZ4HyZS46aeBU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723206; c=relaxed/simple;\n\tbh=v76oLugNliQudaSiLF7raWvFjW25L9D44NNmskeFX5g=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=OugEwLx1ka61oS3JkNQM/VaZ57ywDtBuiupgcFSPtNJBtmF2I67+Z+WCXdTdfljxb0HnXHd5v3amlmTFL07xaB5/2GEs8RcWXt9yXolpiU8nlrtVumckuOoGbtqYWf4s9z3rrECObpSpz2dqVXr+7KK816s6N96frcEIIaFrEAU=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.171", "X-CSE-ConnectionGUID": "sEnIeB9IS+OLzLpESa50Gg==", "X-CSE-MsgGUID": "bxIwQrBMTiGbDUPAIcaPYQ==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 12/16] PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed\n support", "Date": "Tue, 10 Feb 2026 12:30:36 +0100", "Message-ID": "<20260210113041.138430-13-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Extend the link speed configuration to support Gen3 (8.0 GT/s) in addition\nto Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host support, which is\nGen3 capable.\n\nInstead of relying on DT max-link-speed for configuration, read the hardware\ncapabilities from the PCI_EXP_LNKCAP register to determine the maximum\nsupported speed. The DT max-link-speed property is now only used as an\noptional limit when explicitly specified, which aligns with PCIe subsystem\nexpectations.\n\nReviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: No changes\nv4: No changes\nv3: No changes\nv2: Collected tag.\n\n drivers/pci/controller/pcie-rzg3s-host.c | 26 ++++++++++++++++++------\n 1 file changed, 20 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 9368d5c35f30..22858a876fd8 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -977,8 +977,9 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)\n {\n \tu32 remote_supported_link_speeds, max_supported_link_speeds;\n \tu32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC;\n-\tu32 cur_link_speed, link_speed;\n+\tu32 cur_link_speed, link_speed, hw_max_speed;\n \tu8 ltssm_state_l0 = 0xc;\n+\tu32 lnkcap;\n \tint ret;\n \tu16 ls;\n \n@@ -998,7 +999,22 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)\n \tls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);\n \tcs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);\n \n-\tswitch (pcie_link_speed[host->max_link_speed]) {\n+\t/* Read hardware supported link speed from Link Capabilities Register */\n+\tlnkcap = readl_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKCAP);\n+\thw_max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lnkcap);\n+\n+\t/*\n+\t * Use DT max-link-speed only as a limit. If specified and lower\n+\t * than hardware capability, cap to that value.\n+\t */\n+\tif (host->max_link_speed > 0 && host->max_link_speed < hw_max_speed)\n+\t\thw_max_speed = host->max_link_speed;\n+\n+\tswitch (pcie_link_speed[hw_max_speed]) {\n+\tcase PCIE_SPEED_8_0GT:\n+\t\tmax_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_8_0GB - 1, 0);\n+\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;\n+\t\tbreak;\n \tcase PCIE_SPEED_5_0GT:\n \t\tmax_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);\n \t\tlink_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;\n@@ -1014,10 +1030,10 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)\n \tremote_supported_link_speeds &= max_supported_link_speeds;\n \n \t/*\n-\t * Return if max link speed is already set or the connected device\n+\t * Return if target link speed is already set or the connected device\n \t * doesn't support it.\n \t */\n-\tif (cur_link_speed == host->max_link_speed ||\n+\tif (cur_link_speed == hw_max_speed ||\n \t remote_supported_link_speeds != max_supported_link_speeds)\n \t\treturn 0;\n \n@@ -1604,8 +1620,6 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \thost->pcie = host->axi + RZG3S_PCI_CFG_BASE;\n \n \thost->max_link_speed = of_pci_get_max_link_speed(np);\n-\tif (host->max_link_speed < 0)\n-\t\thost->max_link_speed = 2;\n \n \tret = rzg3s_pcie_host_parse_port(host);\n \tif (ret)\n", "prefixes": [ "v5", "12/16" ] }