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GET /api/patches/2195014/?format=api
{ "id": 2195014, "url": "http://patchwork.ozlabs.org/api/patches/2195014/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-12-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-12-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:35", "name": "[v5,11/16] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "708ba08223e87ff5d5ba106f2ce4f9b815b7bb6d", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-12-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195014/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195014/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47078-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-47078-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.172", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KFK2k67z1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:25 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id ED7DE300C358\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:22 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id AE2A93191DE;\n\tTue, 10 Feb 2026 11:33:19 +0000 (UTC)", "from relmlie6.idc.renesas.com (relmlor2.renesas.com\n [210.160.252.172])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1CB07188713;\n\tTue, 10 Feb 2026 11:33:17 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie6.idc.renesas.com with ESMTP; 10 Feb 2026 20:33:17 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id F2BBA41A119E;\n\tTue, 10 Feb 2026 20:33:11 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723199; cv=none;\n b=Uyb9p7wfxJEBJLx+cx/G3iM6zEs+5tNOzxvYTY3Ou6g9Q9NQQtbRpE/gaKRXD7zZttAEGmsIOZgPiEe4XzL8fNhncSFTIjL+QXACPQGjHeN+bKthB4iMMTJT0KboRQIfDfrMTjKKGZ0+YCqoihm9cEih9QAHCIWQ9UVH8M+nIiA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723199; c=relaxed/simple;\n\tbh=MTFAYNwmZsRC66wJ6BNXtZ5hJ6S+PoUXv7XHdYoq1vI=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=ZWj/SXUlY44zEe2fGYrkURtoqHCryVqFUzkuDFu9+qLXF3mzN9psT96Uzh6AW09Koe5lGcFCe4cN3gINlBEPYPepmXiy2pbpgqPXXcXaLKMNpxvLriWBtDyEF9ZGwuzYulrq+IrdWbCdMDNZxZsvcud/tFqm7RCiehmKc66Ab/Q=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "SesvcRjeSkCLKftpbA+WOg==", "X-CSE-MsgGUID": "tAdOTuZ6RQaAy86XCfyBcw==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 11/16] PCI: rzg3s-host: Explicitly set class code for\n RZ/G3E compatibility", "Date": "Tue, 10 Feb 2026 12:30:35 +0100", "Message-ID": "<20260210113041.138430-12-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Program the class code register explicitly during PCIe configuration\ninitialization. RZ/G3E requires this register to be set, while RZ/G3S\nhas these values as hardware defaults.\n\nThis configuration is harmless for RZ/G3S where these match the hardware\ndefaults, and necessary for RZ/G3E to properly identify the device as a\nPCI bridge.\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5:\n - Used field_prep for non-constant mask to fix test robot warnings\n\nv4: No changes\nv3: No changes\nv2: No changes\n\n drivers/pci/controller/pcie-rzg3s-host.c | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 597c233ce297..9368d5c35f30 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -1054,6 +1054,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host)\n static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)\n {\n \tstruct pci_host_bridge *bridge = pci_host_bridge_from_priv(host);\n+\tu32 mask = GENMASK(31, 8);\n \tstruct resource_entry *ft;\n \tstruct resource *bus;\n \tu8 subordinate_bus;\n@@ -1077,6 +1078,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)\n \twritel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L);\n \twritel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U);\n \n+\t/*\n+\t * Explicitly program class code. RZ/G3E requires this configuration.\n+\t * Harmless for RZ/G3S where this matches the hardware default.\n+\t */\n+\trzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask,\n+\t\t\t field_prep(mask, PCI_CLASS_BRIDGE_PCI_NORMAL));\n+\n \t/* Disable access control to the CFGU */\n \twritel_relaxed(0, host->axi + RZG3S_PCI_PERM);\n \n", "prefixes": [ "v5", "11/16" ] }