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GET /api/patches/2195013/?format=api
{ "id": 2195013, "url": "http://patchwork.ozlabs.org/api/patches/2195013/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-11-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-11-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:34", "name": "[v5,10/16] PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a500fbf7a0ae1511fa931aaf3bf762a722b63498", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-11-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195013/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195013/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47077-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-47077-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.172", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KFC3Vnwz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:19 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 89DBF3010636\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:16 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1451D318BAF;\n\tTue, 10 Feb 2026 11:33:14 +0000 (UTC)", "from relmlie6.idc.renesas.com (relmlor2.renesas.com\n [210.160.252.172])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 54238188713;\n\tTue, 10 Feb 2026 11:33:11 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie6.idc.renesas.com with ESMTP; 10 Feb 2026 20:33:11 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id EEA5E41A1194;\n\tTue, 10 Feb 2026 20:33:05 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723194; cv=none;\n b=a3sgV0bdc6Xp5K/spmxMXNCUr5piVrYA3JuEXNn9nCfbNEOqxl5DwHnmPCjmOhCad/4eAslldpRWVcrcJ1mJITQ99HgDDPkOswIP+ds1k+0SCW1+IMfqK/pWJdL18gVJVMgjcWm3IPpHjsN5uRGg+8AepWLFMnLnMmb9AYoS7Vk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723194; c=relaxed/simple;\n\tbh=CXh0EgYgBsfGtKrRm+BULfKTTPmJKkfcV4YPARAG62M=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=unHwxVj223NdYuswSIYa3lNAkkEAt/cN371sE+LOfLwxDnlDU85tRi1/AfEprZycwS79Vzv0CaKGTQfG2O1NrDw0FLkLrgeMJjp6xVJwoJ5B4OkboUL7uDbYKcEPjOSdgmaIGel1hN/gRYfQkwLZWEC+MM5kLZBypBGIDAlaaY4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "ptzByEmATKSqOW9cSgcFAw==", "X-CSE-MsgGUID": "mKBwpSL4SJeb/8vzLaHFoA==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 10/16] PCI: rzg3s-host: Add SoC-specific configuration and\n initialization callbacks", "Date": "Tue, 10 Feb 2026 12:30:34 +0100", "Message-ID": "<20260210113041.138430-11-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks\nto handle SoC-specific configuration methods. While RZ/G3S uses the Linux\nreset framework with dedicated reset lines, other SoC variants like RZ/G3E\ncontrol configuration resets through PCIe AXI registers.\n\nAs Linux reset bulk API gracefully handles optional NULL reset lines\n(num_cfg_resets = 0 for RZ/G3E), the driver continues to use the standard\nreset framework when reset lines are available, while custom callbacks\nare only invoked when provided.\n\nThis provides a balanced pattern where:\n- RZ/G3S: Uses reset framework only, no callbacks needed\n- RZ/G3E: Sets num_cfg_resets=0, provides cfg_pre_init/cfg_post_init/cfg_deinit\n- In addition to that, RZ/G3E requires explicit cfg reset and clock turned off\n to put the PCIe IP in a known state.\n\nAdd cfg_pre_init, cfg_post_init, and cfg_deinit callbacks to support\ncustom configuration mechanism in preparation to RZ/G3E PCIe support.\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5:\n - Roerder got labels as per Claudiu's requirements\n\nv4: No changes\n\nv3: No changes\n\nv2:\n - Renamed callbacks as per Claudiu's comments\n - Reworded goto labels to be consistents with callbacks\n\n drivers/pci/controller/pcie-rzg3s-host.c | 59 +++++++++++++++++-------\n 1 file changed, 42 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 2cac4b68c0cb..597c233ce297 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -223,6 +223,9 @@ struct rzg3s_pcie_host;\n /**\n * struct rzg3s_pcie_soc_data - SoC specific data\n * @init_phy: PHY initialization function\n+ * @config_pre_init: Optional callback for SoC-specific pre-configuration\n+ * @config_post_init: Callback for SoC-specific post-configuration\n+ * @config_deinit: Callback for SoC-specific de-initialization\n * @power_resets: array with the resets that need to be de-asserted after\n * power-on\n * @cfg_resets: array with the resets that need to be de-asserted after\n@@ -233,6 +236,9 @@ struct rzg3s_pcie_host;\n */\n struct rzg3s_pcie_soc_data {\n \tint (*init_phy)(struct rzg3s_pcie_host *host);\n+\tvoid (*config_pre_init)(struct rzg3s_pcie_host *host);\n+\tint (*config_post_init)(struct rzg3s_pcie_host *host);\n+\tint (*config_deinit)(struct rzg3s_pcie_host *host);\n \tconst char * const *power_resets;\n \tconst char * const *cfg_resets;\n \tstruct rzg3s_sysc_info sysc_info;\n@@ -1082,6 +1088,18 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host)\n \treturn 0;\n }\n \n+static int rzg3s_config_post_init(struct rzg3s_pcie_host *host)\n+{\n+\treturn reset_control_bulk_deassert(host->data->num_cfg_resets,\n+\t\t\t\t\t host->cfg_resets);\n+}\n+\n+static int rzg3s_config_deinit(struct rzg3s_pcie_host *host)\n+{\n+\treturn reset_control_bulk_assert(host->data->num_cfg_resets,\n+\t\t\t\t\t host->cfg_resets);\n+}\n+\n static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host)\n {\n \t/*\n@@ -1229,22 +1247,26 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)\n \tu32 val;\n \tint ret;\n \n+\t/* SoC-specific pre-configuration */\n+\tif (host->data->config_pre_init)\n+\t\thost->data->config_pre_init(host);\n+\n \t/* Initialize the PCIe related registers */\n \tret = rzg3s_pcie_config_init(host);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto config_deinit;\n \n \tret = rzg3s_pcie_host_init_port(host);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto config_deinit;\n \n \t/* Initialize the interrupts */\n \trzg3s_pcie_irq_init(host);\n \n-\tret = reset_control_bulk_deassert(host->data->num_cfg_resets,\n-\t\t\t\t\t host->cfg_resets);\n+\t/* SoC-specific post-configuration */\n+\tret = host->data->config_post_init(host);\n \tif (ret)\n-\t\tgoto disable_port_refclk;\n+\t\tgoto config_deinit_and_refclk;\n \n \t/* Wait for link up */\n \tret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val,\n@@ -1253,18 +1275,20 @@ static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host)\n \t\t\t\t PCIE_LINK_WAIT_SLEEP_MS * MILLI *\n \t\t\t\t PCIE_LINK_WAIT_MAX_RETRIES);\n \tif (ret)\n-\t\tgoto cfg_resets_deassert;\n+\t\tgoto config_deinit_post;\n \n \tval = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);\n \tdev_info(host->dev, \"PCIe link status [0x%x]\\n\", val);\n \n \treturn 0;\n \n-cfg_resets_deassert:\n-\treset_control_bulk_assert(host->data->num_cfg_resets,\n-\t\t\t\t host->cfg_resets);\n-disable_port_refclk:\n+config_deinit_post:\n+\thost->data->config_deinit(host);\n+config_deinit_and_refclk:\n \tclk_disable_unprepare(host->port.refclk);\n+config_deinit:\n+\tif (host->data->config_pre_init)\n+\t\thost->data->config_deinit(host);\n \treturn ret;\n }\n \n@@ -1627,7 +1651,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \n host_probe_teardown:\n \trzg3s_pcie_teardown_irqdomain(host);\n-\treset_control_bulk_assert(host->data->num_cfg_resets, host->cfg_resets);\n+\thost->data->config_deinit(host);\n rpm_put:\n \tpm_runtime_put_sync(dev);\n rpm_disable:\n@@ -1662,15 +1686,15 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n \n \tclk_disable_unprepare(port->refclk);\n \n-\tret = reset_control_bulk_assert(data->num_cfg_resets,\n-\t\t\t\t\thost->cfg_resets);\n+\t/* SoC-specific de-initialization */\n+\tret = data->config_deinit(host);\n \tif (ret)\n \t\tgoto refclk_restore;\n \n \tret = reset_control_bulk_assert(data->num_power_resets,\n \t\t\t\t\thost->power_resets);\n \tif (ret)\n-\t\tgoto cfg_resets_restore;\n+\t\tgoto config_reinit;\n \n \tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n \t\t\t\t sysc->info->rst_rsm_b.mask,\n@@ -1684,9 +1708,8 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n power_resets_restore:\n \treset_control_bulk_deassert(data->num_power_resets,\n \t\t\t\t host->power_resets);\n-cfg_resets_restore:\n-\treset_control_bulk_deassert(data->num_cfg_resets,\n-\t\t\t\t host->cfg_resets);\n+config_reinit:\n+\tdata->config_post_init(host);\n refclk_restore:\n \tclk_prepare_enable(port->refclk);\n \tpm_runtime_resume_and_get(dev);\n@@ -1755,6 +1778,8 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {\n \t.num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets),\n \t.cfg_resets = rzg3s_soc_cfg_resets,\n \t.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),\n+\t.config_post_init = rzg3s_config_post_init,\n+\t.config_deinit = rzg3s_config_deinit,\n \t.init_phy = rzg3s_soc_pcie_init_phy,\n \t.sysc_info = {\n \t\t.rst_rsm_b = {\n", "prefixes": [ "v5", "10/16" ] }