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{
    "id": 2195012,
    "url": "http://patchwork.ozlabs.org/api/patches/2195012/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-10-john.madieu.xa@bp.renesas.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
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    "msgid": "<20260210113041.138430-10-john.madieu.xa@bp.renesas.com>",
    "list_archive_url": null,
    "date": "2026-02-10T11:30:33",
    "name": "[v5,09/16] PCI: rzg3s-host: Reorder reset assertion during suspend",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "8650eb0bad7bd13661e161e5974bb8358144c712",
    "submitter": {
        "id": 89876,
        "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api",
        "name": "John Madieu",
        "email": "john.madieu.xa@bp.renesas.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-10-john.madieu.xa@bp.renesas.com/mbox/",
    "series": [
        {
            "id": 491658,
            "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658",
            "date": "2026-02-10T11:30:24",
            "name": "PCI: renesas: Add RZ/G3E PCIe controller support",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2195012/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2195012/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-CSE-MsgGUID": "pjN9xG4wQBORudTQfSYuWw==",
        "From": "John Madieu <john.madieu.xa@bp.renesas.com>",
        "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org",
        "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>",
        "Subject": "[PATCH v5 09/16] PCI: rzg3s-host: Reorder reset assertion during\n suspend",
        "Date": "Tue, 10 Feb 2026 12:30:33 +0100",
        "Message-ID": "<20260210113041.138430-10-john.madieu.xa@bp.renesas.com>",
        "X-Mailer": "git-send-email 2.43.0",
        "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>",
        "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-pci@vger.kernel.org",
        "List-Id": "<linux-pci.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>",
        "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit"
    },
    "content": "Reorder the reset assertion sequence during suspend from\npower_resets -> cfg_resets to cfg_resets -> power_resets.\nThis change ensures the suspend sequence follows the reverse order\nof the probe/init sequence, where power_resets are deasserted first\nfollowed by cfg_resets.\n\nAdditionally, this ordering is required for RZ/G3E support where\ncfg resets are controlled through PCIe AXI registers (offset 0x310h).\nAccording to the RZ/G3E hardware manual (Rev.1.15, section 6.6.6.1.1\n\"Changing the Initial Values of the Registers\"), AXI register access\nrequires ARESETn to be de-asserted and the clock to be supplied.\nSince ARESETn is part of power_resets, cfg_resets must be asserted\nbefore power_resets, otherwise the AXI registers become inaccessible.\n\nFor RZ/G3S, both reset types are CPG-controlled, so the order change\nhas no functional impact.\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: New patch as per Claudiu requirement\n\n drivers/pci/controller/pcie-rzg3s-host.c | 18 +++++++++---------\n 1 file changed, 9 insertions(+), 9 deletions(-)",
    "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex b3b7db93298d..2cac4b68c0cb 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -1662,31 +1662,31 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n \n \tclk_disable_unprepare(port->refclk);\n \n-\tret = reset_control_bulk_assert(data->num_power_resets,\n-\t\t\t\t\thost->power_resets);\n+\tret = reset_control_bulk_assert(data->num_cfg_resets,\n+\t\t\t\t\thost->cfg_resets);\n \tif (ret)\n \t\tgoto refclk_restore;\n \n-\tret = reset_control_bulk_assert(data->num_cfg_resets,\n-\t\t\t\t\thost->cfg_resets);\n+\tret = reset_control_bulk_assert(data->num_power_resets,\n+\t\t\t\t\thost->power_resets);\n \tif (ret)\n-\t\tgoto power_resets_restore;\n+\t\tgoto cfg_resets_restore;\n \n \tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n \t\t\t\t sysc->info->rst_rsm_b.mask,\n \t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n \tif (ret)\n-\t\tgoto cfg_resets_restore;\n+\t\tgoto power_resets_restore;\n \n \treturn 0;\n \n \t/* Restore the previous state if any error happens */\n-cfg_resets_restore:\n-\treset_control_bulk_deassert(data->num_cfg_resets,\n-\t\t\t\t    host->cfg_resets);\n power_resets_restore:\n \treset_control_bulk_deassert(data->num_power_resets,\n \t\t\t\t    host->power_resets);\n+cfg_resets_restore:\n+\treset_control_bulk_deassert(data->num_cfg_resets,\n+\t\t\t\t    host->cfg_resets);\n refclk_restore:\n \tclk_prepare_enable(port->refclk);\n \tpm_runtime_resume_and_get(dev);\n",
    "prefixes": [
        "v5",
        "09/16"
    ]
}