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GET /api/patches/2195011/?format=api
{ "id": 2195011, "url": "http://patchwork.ozlabs.org/api/patches/2195011/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-5-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-5-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:28", "name": "[v5,04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d66354fa86e18c3f78b800a388f68f2a41c88897", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-5-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195011/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47071-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-47071-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.172", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KF53FWsz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:13 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 80C0F3052B96\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:32:36 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E7C2E30F7EB;\n\tTue, 10 Feb 2026 11:32:35 +0000 (UTC)", "from relmlie6.idc.renesas.com (relmlor2.renesas.com\n [210.160.252.172])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 528C7188713;\n\tTue, 10 Feb 2026 11:32:34 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie6.idc.renesas.com with ESMTP; 10 Feb 2026 20:32:34 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 72A0E41A118C;\n\tTue, 10 Feb 2026 20:32:28 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723155; cv=none;\n b=Isu6jqp1mgEq424TqhPpxHVnxyCp087gTlO3LneC2DmRKJi22Eg4xb2lA0nxsV7MGjrWNfaRPxlnJQVFVP0T/fTpNuQHK9nRfLUqhLEcH5wXEUzQgJPFKrYC3z1AOP/ffMFPlaE/cmF6bm+QD9j79x2doJrLY4vhMJcwGyVKpXU=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723155; c=relaxed/simple;\n\tbh=a7A/rEqNhe3ShuPTlkAS8IGB/KJHBbV7qQQSDgnRIVU=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=jFUovWqTt0pN5IFKR2U1gXfzCEWmg9iiOFF1W8Epf1tkUMUhEXTX6pgZGKoa8dE1K3mqm5q+Btxqt56LhL4vnTi9ucnDQXtS6GEdbgNHQJszyNhHlg8g54QH8lsqdyMI6Z+C6TFHg1zXHBKfc7DXvWaqPK/Op50gIuE/fk/FGPs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "y8DxCip1Sj2wCMj0fDzloQ==", "X-CSE-MsgGUID": "1V81IrXxRwGdJ9wIxqShpg==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 04/16] clk: renesas: r9a09g047: Add PCIe clocks and reset", "Date": "Tue, 10 Feb 2026 12:30:28 +0100", "Message-ID": "<20260210113041.138430-5-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Add necessary clocks and reset entries for the PCIe controller\n\nReviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: No changes\nv4: No changes\n\nv3:\n - Collected Rb tag\n - Preserved sort order (by _onindex, _onbit); \n\nv2:\n - Fixed clock names\n - Used assert-variant for reset\n\n drivers/clk/renesas/r9a09g047-cpg.c | 5 +++++\n 1 file changed, 5 insertions(+)", "diff": "diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c\nindex 1e9896742a06..567169194ee8 100644\n--- a/drivers/clk/renesas/r9a09g047-cpg.c\n+++ b/drivers/clk/renesas/r9a09g047-cpg.c\n@@ -424,6 +424,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {\n \t\t\t\t\t\tBUS_MSTOP(8, BIT(6))),\n \tDEF_MOD(\"gbeth_1_aclk_i\",\t\tCLK_PLLDTY_DIV8, 12, 3, 6, 3,\n \t\t\t\t\t\tBUS_MSTOP(8, BIT(6))),\n+\tDEF_MOD_INIT_OFF(\"pcie_0_aclk\",\t\tCLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,\n+\t\t\t\t\t\tBUS_MSTOP(1, BIT(15))),\n+\tDEF_MOD_INIT_OFF(\"pcie_0_clk_pmu\",\tCLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,\n+\t\t\t\t\t\tBUS_MSTOP(1, BIT(15))),\n \tDEF_MOD(\"cru_0_aclk\",\t\t\tCLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,\n \t\t\t\t\t\tBUS_MSTOP(9, BIT(4))),\n \tDEF_MOD_NO_PM(\"cru_0_vclk\",\t\tCLK_PLLVDO_CRU0, 13, 3, 6, 19,\n@@ -503,6 +507,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {\n \tDEF_RST(10, 15, 5, 0),\t\t/* USB2_0_PRESETN */\n \tDEF_RST(11, 0, 5, 1),\t\t/* GBETH_0_ARESETN_I */\n \tDEF_RST(11, 1, 5, 2),\t\t/* GBETH_1_ARESETN_I */\n+\tDEF_RST_INIT_ASSERTED(11, 2, 5, 3),\t\t/* PCIE_0_ARESETN */\n \tDEF_RST(12, 5, 5, 22),\t\t/* CRU_0_PRESETN */\n \tDEF_RST(12, 6, 5, 23),\t\t/* CRU_0_ARESETN */\n \tDEF_RST(12, 7, 5, 24),\t\t/* CRU_0_S_RESETN */\n", "prefixes": [ "v5", "04/16" ] }