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GET /api/patches/2195010/?format=api
{ "id": 2195010, "url": "http://patchwork.ozlabs.org/api/patches/2195010/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-9-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-9-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:32", "name": "[v5,08/16] PCI: rzg3s-host: Make configuration reset lines optional", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f5e76cbc1c2867af53ee0f4e5ac2f15708a4565a", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-9-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195010/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195010/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47075-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-47075-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.172", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KDz4TyTz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:07 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 784233038D12\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:33:05 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id C27CD318EEC;\n\tTue, 10 Feb 2026 11:33:01 +0000 (UTC)", "from relmlie6.idc.renesas.com (relmlor2.renesas.com\n [210.160.252.172])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 290C8314B77;\n\tTue, 10 Feb 2026 11:33:00 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie6.idc.renesas.com with ESMTP; 10 Feb 2026 20:32:59 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 71BD341A118C;\n\tTue, 10 Feb 2026 20:32:53 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723181; cv=none;\n b=b46jrhEQPaqw1ZtqNu+cjJZicSkZCWsjKQEfu+kcAh9iNimyDY697bcHTpzH0/ygSFsJIdIWEk7TlZoCeraehPSDPFPS2rJWYEoknQY5qFF2v7EuyUSCCwhPA6CzMLnX7zKIGK4gUDZAtVXYUcDMrlGJN6pQdA4GJbGDY0EUbH4=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723181; c=relaxed/simple;\n\tbh=qwVdWqpcTBe4Y4Xc4x9oFHlPMdSld+rpOnI8HePeOYY=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=PFeCjtQIDh0YEj01U9nWS0YBYTPWqi3aWfhMEQZoIziS95DgY9YSpF8N7H9R3wcoDnIuoytBA2vNNslD3CTOf7eFikDPl0i3ho66cwDx5nQyyPdXEtQZ8E8ddTIVfo57UgC+CXFDmjb5e242279e7DeKXGc/nK1oEOOI/trWJxs=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "VBEtuXZATbe+Bh0QA05/LA==", "X-CSE-MsgGUID": "BBoB6ci5THqyYLgn1pWE6A==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 08/16] PCI: rzg3s-host: Make configuration reset lines\n optional", "Date": "Tue, 10 Feb 2026 12:30:32 +0100", "Message-ID": "<20260210113041.138430-9-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Some SoC variants such as RZ/G3E handle configuration reset control\nthrough PCIe AXI registers instead of dedicated reset lines. Make cfg_resets\noptional by using devm_reset_control_bulk_get_optional_exclusive() to allow\nSoCs to use alternative or complementary reset control mechanisms.\n\nReviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nchanges:\n\nv5: No changes\nv4: No changes\nv3: No changes\nv2: Collected Rb tag.\n\n drivers/pci/controller/pcie-rzg3s-host.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 8f80484bb85e..b3b7db93298d 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -1161,9 +1161,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host)\n \tif (ret)\n \t\treturn ret;\n \n-\treturn devm_reset_control_bulk_get_exclusive(host->dev,\n-\t\t\t\t\t\t data->num_cfg_resets,\n-\t\t\t\t\t\t host->cfg_resets);\n+\treturn devm_reset_control_bulk_get_optional_exclusive(host->dev,\n+\t\t\t\t\t\t\t data->num_cfg_resets,\n+\t\t\t\t\t\t\t host->cfg_resets);\n }\n \n static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)\n", "prefixes": [ "v5", "08/16" ] }