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GET /api/patches/2195009/?format=api
{ "id": 2195009, "url": "http://patchwork.ozlabs.org/api/patches/2195009/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-3-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-3-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:26", "name": "[v5,02/16] PCI: renesas: rzg3s: Rework inbound window algorithm for multi-SoC support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1144f4893ed4da77f0629a5fd25f43c84662ffe1", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-3-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195009/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195009/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47069-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-47069-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.171", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KDs15xZz1xwH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:01 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 7A59D3046EA0\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:32:31 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3934CA59;\n\tTue, 10 Feb 2026 11:32:30 +0000 (UTC)", "from relmlie5.idc.renesas.com (relmlor1.renesas.com\n [210.160.252.171])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 338DD2DAFC2;\n\tTue, 10 Feb 2026 11:32:27 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie5.idc.renesas.com with ESMTP; 10 Feb 2026 20:32:21 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 03D5B41A118C;\n\tTue, 10 Feb 2026 20:32:15 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723150; cv=none;\n b=X0jlS1Ur7/7XX/GJKvKwkfRAMGTO49WgwqavDTPemfT3X1SbiCWjgm9C997cLMVd/FFy3RP6E35YGzjqPMKmwKL08JfhRmIUL9RqK1fGtznKurzyCUezXVAk5zJvl8yNCAzSAfdrBPwa+9FUVdiWAGWt+Qd7xCizM02i37kGo4Q=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723150; c=relaxed/simple;\n\tbh=8iwpb+uJrGRvsAHVAxxbvzSj7cJmqyImwq9JcakA9BY=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=nyK3RXNw6wkni4/HydEi+wADyqB20f8oPr/vA98W0KZuN5hD+x0WD7KM9kGQnR7y7jD0r6BDCIcjBJfVB6yR15twSqWhkab6eyvhDEezdJRJTvDrtYj2KopAczm/gXd4Ht3hIAfgxd8E2kXYPgMABeZ7ZhZoZYbGI0twra3oBXk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.171", "X-CSE-ConnectionGUID": "eigSGyuWTCuVSpLDk41dRg==", "X-CSE-MsgGUID": "JVw1J3AjSce6i7FPzQYo+g==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 02/16] PCI: renesas: rzg3s: Rework inbound window algorithm\n for multi-SoC support", "Date": "Tue, 10 Feb 2026 12:30:26 +0100", "Message-ID": "<20260210113041.138430-3-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "The existing inbound window configuration algorithm has two issues that\nprevent proper operation on RZ/G3E:\n\n1. Over-mapping: Using roundup_pow_of_two() on the remaining region size\n can result in windows that extend beyond the intended memory region.\n\n2. Alignment violation: Addresses are only aligned to 4K regardless of\n the actual window size. According to the RZ/G3S HW manual (Rev.1.10,\n section 34.6.6.7) and RZ/G3E HW manual (Rev.1.15, section 6.6.7.6),\n bit carry must not occur when adding AXI Window Base and AXI Window\n Mask registers. This effectively requires the base address to be\n aligned to the window size.\n\nRZ/G3E strictly enforces these constraints and requires precise window\nboundaries with properly aligned addresses.\n\nRework the algorithm to properly handle arbitrary region sizes and\nalignment constraints by splitting non-power-of-2 regions into multiple\nwindows. The new approach iteratively selects the largest power-of-2\nsize that:\n - Fits within the remaining region (__fls of remaining size)\n - Does not exceed the natural alignment of the CPU address (__ffs)\n - Does not exceed the natural alignment of the PCI address (__ffs)\n\nThis ensures windows never over-map beyond the intended region and\nsatisfies the hardware requirement that base address + mask must not\ncause bit carry, while maintaining the 4K * 2^N byte window size\nconstraint.\n\nThe reworked algorithm is required for RZ/G3E support and remains\nfully compatible with RZ/G3S.\n\nReviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5:\n - Updated HW manual section specification\n - Collected Rb tag\n\nv4: No changes\nv3: No changes\nv2: New patch\n\n drivers/pci/controller/pcie-rzg3s-host.c | 53 +++++++++++++-----------\n 1 file changed, 29 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 58e78fc52913..8ccf55d019cf 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -1270,50 +1270,55 @@ static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host,\n \tu64 pci_addr = entry->res->start - entry->offset;\n \tu64 cpu_addr = entry->res->start;\n \tu64 cpu_end = entry->res->end;\n-\tu64 size_id = 0;\n \tint id = *index;\n \tu64 size;\n \n-\twhile (cpu_addr < cpu_end) {\n+\t/*\n+\t * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.6.7) and\n+\t * RZ/G3E HW manual (Rev.1.15, section 6.6.7.6):\n+\t * - Each window must be a single memory size of power of two\n+\t * - Mask registers must be set to (2^N - 1)\n+\t * - Bit carry must not occur when adding base and mask registers,\n+\t * meaning the base address must be aligned to the window size\n+\t *\n+\t * Split non-power-of-2 regions into multiple windows to satisfy\n+\t * these constraints without over-mapping.\n+\t */\n+\twhile (cpu_addr <= cpu_end) {\n+\t\tu64 remaining_size = cpu_end - cpu_addr + 1;\n+\t\tu64 align_limit;\n+\n \t\tif (id >= RZG3S_MAX_WINDOWS)\n \t\t\treturn dev_err_probe(host->dev, -ENOSPC,\n \t\t\t\t\t \"Failed to map inbound window for resource (%s)\\n\",\n \t\t\t\t\t entry->res->name);\n \n-\t\tsize = resource_size(entry->res) - size_id;\n+\t\t/* Start with largest power-of-two that fits in remaining size */\n+\t\tsize = 1ULL << __fls(remaining_size);\n \n \t\t/*\n-\t\t * According to the RZ/G3S HW manual (Rev.1.10,\n-\t\t * section 34.3.1.71 AXI Window Mask (Lower) Registers) the min\n-\t\t * size is 4K.\n+\t\t * The \"no bit carry\" rule requires base addresses to be\n+\t\t * aligned to the window size. Find the maximum window size\n+\t\t * that both addresses can support based on their natural\n+\t\t * alignment (lowest set bit).\n \t\t */\n-\t\tsize = max(size, SZ_4K);\n+\t\talign_limit = min(cpu_addr ? (1ULL << __ffs(cpu_addr)) : ~0ULL,\n+\t\t\t\t pci_addr ? (1ULL << __ffs(pci_addr)) : ~0ULL);\n \n-\t\t/*\n-\t\t * According the RZ/G3S HW manual (Rev.1.10, sections:\n-\t\t * - 34.3.1.69 AXI Window Base (Lower) Registers\n-\t\t * - 34.3.1.71 AXI Window Mask (Lower) Registers\n-\t\t * - 34.3.1.73 AXI Destination (Lower) Registers)\n-\t\t * the CPU addr, PCIe addr, size should be 4K aligned and be a\n-\t\t * power of 2.\n-\t\t */\n-\t\tsize = ALIGN(size, SZ_4K);\n-\t\tsize = roundup_pow_of_two(size);\n-\n-\t\tcpu_addr = ALIGN(cpu_addr, SZ_4K);\n-\t\tpci_addr = ALIGN(pci_addr, SZ_4K);\n+\t\tsize = min(size, align_limit);\n \n \t\t/*\n-\t\t * According to the RZ/G3S HW manual (Rev.1.10, section\n-\t\t * 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first\n-\t\t * 12 LSB bits to be 0xfff. Subtract 1 from size for this.\n+\t\t * Minimum window size is 4KB.\n+\t\t * See RZ/G3S HW manual (Rev.1.10, section 34.3.1.71) and\n+\t\t * RZ/G3E HW manual (Rev.1.15, section 6.6.4.1.3.(74)).\n \t\t */\n+\t\tsize = max(size, SZ_4K);\n+\n \t\trzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr,\n \t\t\t\t\t size - 1, id);\n \n \t\tpci_addr += size;\n \t\tcpu_addr += size;\n-\t\tsize_id = size;\n \t\tid++;\n \t}\n \t*index = id;\n", "prefixes": [ "v5", "02/16" ] }