Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2195008/?format=api
{ "id": 2195008, "url": "http://patchwork.ozlabs.org/api/patches/2195008/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-8-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-8-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:31", "name": "[v5,07/16] PCI: rzg3s-host: Make SYSC register offsets SoC-specific", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "20a0b70604ac5b88ecdf8519be63a59552472bc1", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-8-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195008/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195008/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47074-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-47074-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.171", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KDr2Cjzz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:33:00 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 8A2FA30396B1\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:32:58 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id BDB14314B77;\n\tTue, 10 Feb 2026 11:32:55 +0000 (UTC)", "from relmlie5.idc.renesas.com (relmlor1.renesas.com\n [210.160.252.171])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id BD2BA188713;\n\tTue, 10 Feb 2026 11:32:53 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie5.idc.renesas.com with ESMTP; 10 Feb 2026 20:32:52 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 6074D41A118C;\n\tTue, 10 Feb 2026 20:32:47 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723175; cv=none;\n b=aNBSYtn3zLgUdEpE5A7Y0Mw/CuXIpYt5ee4o5PLgtQHU+ipfG5dS3BQDaeoQlfXI9w36hhCnf8/3ku2+mTFKIwxF/iSZodgVScRojgbftTF+tNRTp6BFG3ciW4m1gda4eoAQT3yp3PWq26w5KvMBh2cSAmyuu+ZM51Rw7MTm0Mk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723175; c=relaxed/simple;\n\tbh=IJvZZ8db5S5XqVkL74rZm334capzMQJuYQhgTihpvWY=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=b+bbEFD5U1tRP+jfA323QJRt6NyeQoo3AKZZnl3QpTGNrCR0UVxJZr5eV567TgWH52dQ/8N9liaiX8qN4uIKKB4+SuWAGqhsLSzFMz3ICqj7pio2F7TU+IyfzHRP1WQnFe8mTwPISMffMlHnwX+Lax06BSvxs+AialANAjQRQkM=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.171", "X-CSE-ConnectionGUID": "WZh6kUAhRWiJRl9rqP5nGQ==", "X-CSE-MsgGUID": "OaxGqN4WRCephFgDukyKUw==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 07/16] PCI: rzg3s-host: Make SYSC register offsets\n SoC-specific", "Date": "Tue, 10 Feb 2026 12:30:31 +0100", "Message-ID": "<20260210113041.138430-8-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "In preparation for adding RZ/G3E support, move the RST_RSM_B register\noffset and mask into a SoC-specific data structure. Compared with RZ/G3S,\nthe RZ/G3E SYSC controls different functionalities for the PCIe controller.\n\nMake SYSC operations conditional on the presence of register offset\ninformation, allowing the driver to handle SoCs that don't use the\nRST_RSM_B signal.\n\nReviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: Collected Rb tag from Claudiu\nv4: No changes\nv3: No changes\nv2: Address Claudiu's styling comment\n\n drivers/pci/controller/pcie-rzg3s-host.c | 92 +++++++++++++++++-------\n 1 file changed, 66 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c\nindex 8ccf55d019cf..8f80484bb85e 100644\n--- a/drivers/pci/controller/pcie-rzg3s-host.c\n+++ b/drivers/pci/controller/pcie-rzg3s-host.c\n@@ -159,10 +159,6 @@\n \n #define RZG3S_PCI_CFG_PCIEC\t\t\t0x60\n \n-/* System controller registers */\n-#define RZG3S_SYS_PCIE_RST_RSM_B\t\t0xd74\n-#define RZG3S_SYS_PCIE_RST_RSM_B_MASK\t\tBIT(0)\n-\n /* Maximum number of windows */\n #define RZG3S_MAX_WINDOWS\t\t\t8\n \n@@ -174,6 +170,34 @@\n /* Timeouts experimentally determined */\n #define RZG3S_REQ_ISSUE_TIMEOUT_US\t\t2500\n \n+/**\n+ * struct rzg3s_sysc_function - System Controller register function descriptor\n+ * @offset: Register offset from the System Controller base address\n+ * @mask: Bit mask for the function within the register\n+ */\n+struct rzg3s_sysc_function {\n+\tu32 offset;\n+\tu32 mask;\n+};\n+\n+/**\n+ * struct rzg3s_sysc_info - RZ/G3S System Controller function info\n+ * @rst_rsm_b: Reset RSM_B function descriptor\n+ */\n+struct rzg3s_sysc_info {\n+\tstruct rzg3s_sysc_function rst_rsm_b;\n+};\n+\n+/**\n+ * struct rzg3s_sysc - RZ/G3S System Controller descriptor\n+ * @regmap: System controller regmap\n+ * @info: System controller info\n+ */\n+struct rzg3s_sysc {\n+\tstruct regmap *regmap;\n+\tconst struct rzg3s_sysc_info *info;\n+};\n+\n /**\n * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure\n * @domain: IRQ domain\n@@ -203,6 +227,7 @@ struct rzg3s_pcie_host;\n * power-on\n * @cfg_resets: array with the resets that need to be de-asserted after\n * configuration\n+ * @sysc_info: SYSC functionalities\n * @num_power_resets: number of power resets\n * @num_cfg_resets: number of configuration resets\n */\n@@ -210,6 +235,7 @@ struct rzg3s_pcie_soc_data {\n \tint (*init_phy)(struct rzg3s_pcie_host *host);\n \tconst char * const *power_resets;\n \tconst char * const *cfg_resets;\n+\tstruct rzg3s_sysc_info sysc_info;\n \tu8 num_power_resets;\n \tu8 num_cfg_resets;\n };\n@@ -233,7 +259,7 @@ struct rzg3s_pcie_port {\n * @dev: struct device\n * @power_resets: reset control signals that should be set after power up\n * @cfg_resets: reset control signals that should be set after configuration\n- * @sysc: SYSC regmap\n+ * @sysc: SYSC descriptor\n * @intx_domain: INTx IRQ domain\n * @data: SoC specific data\n * @msi: MSI data structure\n@@ -248,7 +274,7 @@ struct rzg3s_pcie_host {\n \tstruct device *dev;\n \tstruct reset_control_bulk_data *power_resets;\n \tstruct reset_control_bulk_data *cfg_resets;\n-\tstruct regmap *sysc;\n+\tstruct rzg3s_sysc *sysc;\n \tstruct irq_domain *intx_domain;\n \tconst struct rzg3s_pcie_soc_data *data;\n \tstruct rzg3s_pcie_msi msi;\n@@ -1521,6 +1547,7 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \tstruct device_node *sysc_np __free(device_node) =\n \t\tof_parse_phandle(np, \"renesas,sysc\", 0);\n \tstruct rzg3s_pcie_host *host;\n+\tstruct rzg3s_sysc *sysc;\n \tint ret;\n \n \tbridge = devm_pci_alloc_host_bridge(dev, sizeof(*host));\n@@ -1532,6 +1559,13 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \thost->data = device_get_match_data(dev);\n \tplatform_set_drvdata(pdev, host);\n \n+\thost->sysc = devm_kzalloc(dev, sizeof(*host->sysc), GFP_KERNEL);\n+\tif (!host->sysc)\n+\t\treturn -ENOMEM;\n+\n+\tsysc = host->sysc;\n+\tsysc->info = &host->data->sysc_info;\n+\n \thost->axi = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(host->axi))\n \t\treturn PTR_ERR(host->axi);\n@@ -1545,15 +1579,15 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \tif (ret)\n \t\treturn ret;\n \n-\thost->sysc = syscon_node_to_regmap(sysc_np);\n-\tif (IS_ERR(host->sysc)) {\n-\t\tret = PTR_ERR(host->sysc);\n+\tsysc->regmap = syscon_node_to_regmap(sysc_np);\n+\tif (IS_ERR(sysc->regmap)) {\n+\t\tret = PTR_ERR(sysc->regmap);\n \t\tgoto port_refclk_put;\n \t}\n \n-\tret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,\n-\t\t\t\t RZG3S_SYS_PCIE_RST_RSM_B_MASK,\n-\t\t\t\t FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));\n+\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n+\t\t\t\t sysc->info->rst_rsm_b.mask,\n+\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 1));\n \tif (ret)\n \t\tgoto port_refclk_put;\n \n@@ -1605,9 +1639,9 @@ static int rzg3s_pcie_probe(struct platform_device *pdev)\n \t * SYSC RST_RSM_B signal need to be asserted before turning off the\n \t * power to the PHY.\n \t */\n-\tregmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B,\n-\t\t\t RZG3S_SYS_PCIE_RST_RSM_B_MASK,\n-\t\t\t FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));\n+\tregmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n+\t\t\t sysc->info->rst_rsm_b.mask,\n+\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n port_refclk_put:\n \tclk_put(host->port.refclk);\n \n@@ -1619,7 +1653,7 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n \tstruct rzg3s_pcie_host *host = dev_get_drvdata(dev);\n \tconst struct rzg3s_pcie_soc_data *data = host->data;\n \tstruct rzg3s_pcie_port *port = &host->port;\n-\tstruct regmap *sysc = host->sysc;\n+\tstruct rzg3s_sysc *sysc = host->sysc;\n \tint ret;\n \n \tret = pm_runtime_put_sync(dev);\n@@ -1638,9 +1672,9 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)\n \tif (ret)\n \t\tgoto power_resets_restore;\n \n-\tret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,\n-\t\t\t\t RZG3S_SYS_PCIE_RST_RSM_B_MASK,\n-\t\t\t\t FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));\n+\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n+\t\t\t\t sysc->info->rst_rsm_b.mask,\n+\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n \tif (ret)\n \t\tgoto cfg_resets_restore;\n \n@@ -1663,12 +1697,12 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)\n {\n \tstruct rzg3s_pcie_host *host = dev_get_drvdata(dev);\n \tconst struct rzg3s_pcie_soc_data *data = host->data;\n-\tstruct regmap *sysc = host->sysc;\n+\tstruct rzg3s_sysc *sysc = host->sysc;\n \tint ret;\n \n-\tret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,\n-\t\t\t\t RZG3S_SYS_PCIE_RST_RSM_B_MASK,\n-\t\t\t\t FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1));\n+\tret = regmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n+\t\t\t\t sysc->info->rst_rsm_b.mask,\n+\t\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 1));\n \tif (ret)\n \t\treturn ret;\n \n@@ -1697,9 +1731,9 @@ static int rzg3s_pcie_resume_noirq(struct device *dev)\n \treset_control_bulk_assert(data->num_power_resets,\n \t\t\t\t host->power_resets);\n assert_rst_rsm_b:\n-\tregmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,\n-\t\t\t RZG3S_SYS_PCIE_RST_RSM_B_MASK,\n-\t\t\t FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));\n+\tregmap_update_bits(sysc->regmap, sysc->info->rst_rsm_b.offset,\n+\t\t\t sysc->info->rst_rsm_b.mask,\n+\t\t\t field_prep(sysc->info->rst_rsm_b.mask, 0));\n \treturn ret;\n }\n \n@@ -1722,6 +1756,12 @@ static const struct rzg3s_pcie_soc_data rzg3s_soc_data = {\n \t.cfg_resets = rzg3s_soc_cfg_resets,\n \t.num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets),\n \t.init_phy = rzg3s_soc_pcie_init_phy,\n+\t.sysc_info = {\n+\t\t.rst_rsm_b = {\n+\t\t\t.offset = 0xd74,\n+\t\t\t.mask = BIT(0),\n+\t\t},\n+\t},\n };\n \n static const struct of_device_id rzg3s_pcie_of_match[] = {\n", "prefixes": [ "v5", "07/16" ] }