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GET /api/patches/2195004/?format=api
{ "id": 2195004, "url": "http://patchwork.ozlabs.org/api/patches/2195004/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-4-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-4-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:27", "name": "[v5,03/16] clk: renesas: rzv2h-cpg: Add support for init_{off|asserted} clocks/resets", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "05b2ed26ea19f156dadd92b01d4a27aa208af573", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260210113041.138430-4-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195004/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195004/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47070-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-47070-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=210.160.252.172", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=bp.renesas.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KDM3W1qz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:32:35 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 44160303B96E\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 11:32:32 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 89E55318ED8;\n\tTue, 10 Feb 2026 11:32:30 +0000 (UTC)", "from relmlie6.idc.renesas.com (relmlor2.renesas.com\n [210.160.252.172])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id B9D9130B50F;\n\tTue, 10 Feb 2026 11:32:28 +0000 (UTC)", "from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152])\n by relmlie6.idc.renesas.com with ESMTP; 10 Feb 2026 20:32:27 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 5262C41A118C;\n\tTue, 10 Feb 2026 20:32:22 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723150; cv=none;\n b=TsjDVa/K+7+dcwEUBDdRJG4cEIABkd7PT4MNmcS2z1yHqO7j8BoRy0lbGkIvGJFcZEn760TbgIZWmxuclUNibBpS4PXTL+vZbhPweB3omXA2YqqJXkf/+zsdsRmpLBDl6wMYH9QmVrNNp9RwN7fwPRa0xFcEIxr1eDa7i/CKPKI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723150; c=relaxed/simple;\n\tbh=yEcnUp+7evgTvt29R567zGOTvXzlQn65602Lrx/OFRM=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=o8E2Tnp9MxxAakEozkfpc6gxw3oH1aNo3OJ+TNpcUfYobS2kmuyv3vdmMkJeSfpFzqGpHMvATlN8ruXghuMzMyzSnraO32Cq/vJXgYJBJjdI6PawmaSNDW2uwZyeH1ZMwdyu07d8vzONLGvyZSWAqQIIipLaKIUmIzcL/DyJ6Po=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "oX4fh8e4RDu/QPqIzXyrTA==", "X-CSE-MsgGUID": "kN+ikNIsTOGGcSCz6PCY7w==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 03/16] clk: renesas: rzv2h-cpg: Add support for\n init_{off|asserted} clocks/resets", "Date": "Tue, 10 Feb 2026 12:30:27 +0100", "Message-ID": "<20260210113041.138430-4-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "References": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Some peripherals may be left enabled by the bootloader but should be\nexplicitly disabled by the kernel to ensure a known initial state.\nThis is particularly important for PCIe which requires proper\ninitialization sequencing.\n\nAdd new macros DEF_MOD_INIT_OFF() and DEF_RST_INIT_ASSERTED() to declare\nmodule clocks that should be turned off and resets that should be\nasserted during CPG probe if found in the opposite state.\n\nSigned-off-by: John Madieu <john.madieu.xa@bp.renesas.com>\n---\n\nChanges:\n\nv5: No changes\nv4: No changes\n\nv3: \n - Fixed potential unitialized rcdev crash\n - Removed duplicated message\n\nv2:\n - Added reset-specific assert on probe\n - Removed Rb tag from Geert due to previous point\n\n drivers/clk/renesas/rzv2h-cpg.c | 24 ++++++++++++++++++++++-\n drivers/clk/renesas/rzv2h-cpg.h | 34 +++++++++++++++++++++++++--------\n 2 files changed, 49 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c\nindex 3f6299b9fec0..8e45f6f48e29 100644\n--- a/drivers/clk/renesas/rzv2h-cpg.c\n+++ b/drivers/clk/renesas/rzv2h-cpg.c\n@@ -1337,6 +1337,13 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,\n \t\tspin_unlock_irqrestore(&priv->rmw_lock, flags);\n \t}\n \n+\t/*\n+\t * Turn off clocks marked with init_off flag if they were left\n+\t * enabled by the bootloader. This ensures a known initial state.\n+\t */\n+\tif (mod->init_off && rzv2h_mod_clock_is_enabled(&clock->hw))\n+\t\trzv2h_mod_clock_endisable(&clock->hw, false);\n+\n \treturn;\n \n fail:\n@@ -1585,7 +1592,7 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)\n \tstruct rzv2h_cpg_priv *priv;\n \tunsigned int nclks, i;\n \tstruct clk **clks;\n-\tint error;\n+\tint error, ret;\n \n \tinfo = of_device_get_match_data(dev);\n \n@@ -1635,6 +1642,21 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)\n \tfor (i = 0; i < info->num_mod_clks; i++)\n \t\trzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);\n \n+\t/*\n+\t * Assert resets marked with init_asserted flag if they were left\n+\t * deasserted by the bootloader. This ensures a known initial state.\n+\t */\n+\tpriv->rcdev.dev = dev;\n+\tfor (i = 0; i < info->num_resets; i++) {\n+\t\tif (!info->resets[i].init_asserted)\n+\t\t\tcontinue;\n+\n+\t\t/* Check if reset is currently deasserted (status == 0) */\n+\t\tret = rzv2h_cpg_status(&priv->rcdev, i);\n+\t\tif (ret == 0)\n+\t\t\trzv2h_cpg_assert(&priv->rcdev, i);\n+\t}\n+\n \terror = of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv);\n \tif (error)\n \t\treturn error;\ndiff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h\nindex dc957bdaf5e9..927009431a73 100644\n--- a/drivers/clk/renesas/rzv2h-cpg.h\n+++ b/drivers/clk/renesas/rzv2h-cpg.h\n@@ -250,6 +250,7 @@ enum clk_types {\n * @parent: id of parent clock\n * @critical: flag to indicate the clock is critical\n * @no_pm: flag to indicate PM is not supported\n+ * @init_off: flag to indicate the clock should be turned off during probe\n * @on_index: control register index\n * @on_bit: ON bit\n * @mon_index: monitor register index\n@@ -262,6 +263,7 @@ struct rzv2h_mod_clk {\n \tu16 parent;\n \tbool critical;\n \tbool no_pm;\n+\tbool init_off;\n \tu8 on_index;\n \tu8 on_bit;\n \ts8 mon_index;\n@@ -269,14 +271,15 @@ struct rzv2h_mod_clk {\n \ts8 ext_clk_mux_index;\n };\n \n-#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \\\n-\t\t _onbit, _monindex, _monbit, _ext_clk_mux_index) \\\n+#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _init_off, \\\n+\t\t _onindex, _onbit, _monindex, _monbit, _ext_clk_mux_index) \\\n \t{ \\\n \t\t.name = (_name), \\\n \t\t.mstop_data = (_mstop), \\\n \t\t.parent = (_parent), \\\n \t\t.critical = (_critical), \\\n \t\t.no_pm = (_no_pm), \\\n+\t\t.init_off = (_init_off), \\\n \t\t.on_index = (_onindex), \\\n \t\t.on_bit = (_onbit), \\\n \t\t.mon_index = (_monindex), \\\n@@ -285,17 +288,20 @@ struct rzv2h_mod_clk {\n \t}\n \n #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \\\n-\tDEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1)\n+\tDEF_MOD_BASE(_name, _mstop, _parent, false, false, false, _onindex, _onbit, _monindex, _monbit, -1)\n \n #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \\\n-\tDEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1)\n+\tDEF_MOD_BASE(_name, _mstop, _parent, true, false, false, _onindex, _onbit, _monindex, _monbit, -1)\n+\n+#define DEF_MOD_INIT_OFF(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \\\n+\tDEF_MOD_BASE(_name, _mstop, _parent, false, false, true, _onindex, _onbit, _monindex, _monbit, -1)\n \n #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \\\n-\tDEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1)\n+\tDEF_MOD_BASE(_name, _mstop, _parent, false, true, false, _onindex, _onbit, _monindex, _monbit, -1)\n \n #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \\\n \t\t\t _ext_clk_mux_index) \\\n-\tDEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \\\n+\tDEF_MOD_BASE(_name, _mstop, _parent, false, false, false, _onindex, _onbit, _monindex, _monbit, \\\n \t\t _ext_clk_mux_index)\n \n /**\n@@ -305,24 +311,36 @@ struct rzv2h_mod_clk {\n * @reset_bit: reset bit\n * @mon_index: monitor register index\n * @mon_bit: monitor bit\n+ * @init_asserted: flag to indicate the reset should be asserted during probe\n */\n struct rzv2h_reset {\n \tu8 reset_index;\n \tu8 reset_bit;\n \tu8 mon_index;\n \tu8 mon_bit;\n+\tbool init_asserted;\n };\n \n-#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)\t\\\n+#define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit, _init_asserted)\t\\\n \t{ \\\n \t\t.reset_index = (_resindex), \\\n \t\t.reset_bit = (_resbit), \\\n \t\t.mon_index = (_monindex), \\\n \t\t.mon_bit = (_monbit), \\\n+\t\t.init_asserted = (_init_asserted), \\\n \t}\n \n #define DEF_RST(_resindex, _resbit, _monindex, _monbit)\t\\\n-\tDEF_RST_BASE(_resindex, _resbit, _monindex, _monbit)\n+\tDEF_RST_BASE(_resindex, _resbit, _monindex, _monbit, false)\n+\n+/**\n+ * DEF_RST_INIT_ASSERTED - Define a reset that should be asserted during probe\n+ *\n+ * Use this for peripherals that require their reset to be asserted at boot\n+ * to ensure a known initial state before the peripheral driver takes over.\n+ */\n+#define DEF_RST_INIT_ASSERTED(_reset_index, _reset_bit, _mon_index, _mon_bit) \\\n+\tDEF_RST_BASE(_reset_index, _reset_bit, _mon_index, _mon_bit, true)\n \n /**\n * struct rzv2h_cpg_info - SoC-specific CPG Description\n", "prefixes": [ "v5", "03/16" ] }