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GET /api/patches/2195001/?format=api
{ "id": 2195001, "url": "http://patchwork.ozlabs.org/api/patches/2195001/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210-phys_addr-v4-8-725a589e83c8@rev.ng/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210-phys_addr-v4-8-725a589e83c8@rev.ng>", "list_archive_url": null, "date": "2026-02-10T11:33:19", "name": "[v4,8/8] Drop TARGET_PHYS_ADDR_SPACE_BITS", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6184fff5d11d82affcaacffaa574c146caa6d0dd", "submitter": { "id": 92408, "url": "http://patchwork.ozlabs.org/api/people/92408/?format=api", "name": "Anton Johansson", "email": "anjo@rev.ng" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210-phys_addr-v4-8-725a589e83c8@rev.ng/mbox/", "series": [ { "id": 491656, "url": "http://patchwork.ozlabs.org/api/series/491656/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491656", "date": "2026-02-10T11:33:12", "name": "single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/491656/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2195001/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2195001/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=rev.ng header.i=@rev.ng header.a=rsa-sha256\n header.s=dkim header.b=HSp8SPjp;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KCS6z2Lz1xwH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:31:48 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vplx2-0005QT-9Y; Tue, 10 Feb 2026 06:30:40 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vplwy-0005P0-LO\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:38 -0500", "from rev.ng ([94.130.142.21])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vplww-0008L8-FB\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:36 -0500" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng;\n s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:\n Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID:\n Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe:\n List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post:\n List-Help; bh=1G5C5mK8Z7iY/p02AMfuk2WS4d5n7ES5YnjTpLmvtLo=; b=HSp8SPjp34iNIdX\n 8lkZ0dd7npEaKa9K0Utbtl9wfVLxBBzbvXGylSl5GiYPyoFiEswR3a0yxxPx8i9ZOV76p/KK/5C3W\n hlOKcuYdqi2N89ZZxZ2xYcCAcm5ZMKYgm+4jDHVarIk1AVcspO7wu6cDFaDJCaoRGv5sNEt67+Miz\n OU=;", "Date": "Tue, 10 Feb 2026 12:33:19 +0100", "Subject": "[PATCH v4 8/8] Drop TARGET_PHYS_ADDR_SPACE_BITS", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260210-phys_addr-v4-8-725a589e83c8@rev.ng>", "References": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>", "In-Reply-To": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>,\n Anton Johansson <anjo@rev.ng>, palmer@dabbelt.com, alistair.francis@wdc.com,\n pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn,\n deller@gmx.de, Brian Cain <brian.cain@oss.qualcomm.com>", "Received-SPF": "pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng;\n helo=rev.ng", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Anton Johansson <anjo@rev.ng>", "From": "Anton Johansson via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The macro is no longer in use and can safely be dropped.\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>\nSigned-off-by: Anton Johansson <anjo@rev.ng>\n---\n include/exec/cpu-defs.h | 3 ---\n include/exec/poison.h | 2 --\n target/alpha/cpu-param.h | 3 ---\n target/arm/cpu-param.h | 2 --\n target/avr/cpu-param.h | 1 -\n target/hexagon/cpu-param.h | 1 -\n target/hppa/cpu-param.h | 3 ---\n target/i386/cpu-param.h | 2 --\n target/loongarch/cpu-param.h | 1 -\n target/m68k/cpu-param.h | 1 -\n target/microblaze/cpu-param.h | 2 --\n target/mips/cpu-param.h | 2 --\n target/openrisc/cpu-param.h | 1 -\n target/ppc/cpu-param.h | 7 -------\n target/riscv/cpu-param.h | 2 --\n target/rx/cpu-param.h | 1 -\n target/s390x/cpu-param.h | 1 -\n target/sh4/cpu-param.h | 1 -\n target/sparc/cpu-param.h | 2 --\n target/tricore/cpu-param.h | 1 -\n target/xtensa/cpu-param.h | 1 -\n 21 files changed, 40 deletions(-)", "diff": "diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h\nindex e01acb7c90..141b5a9929 100644\n--- a/include/exec/cpu-defs.h\n+++ b/include/exec/cpu-defs.h\n@@ -28,9 +28,6 @@\n #ifndef TARGET_LONG_BITS\n # error TARGET_LONG_BITS must be defined in cpu-param.h\n #endif\n-#ifndef TARGET_PHYS_ADDR_SPACE_BITS\n-# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h\n-#endif\n #ifndef TARGET_VIRT_ADDR_SPACE_BITS\n # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h\n #endif\ndiff --git a/include/exec/poison.h b/include/exec/poison.h\nindex a779adbb7a..2caf2d92f1 100644\n--- a/include/exec/poison.h\n+++ b/include/exec/poison.h\n@@ -43,8 +43,6 @@\n #pragma GCC poison TARGET_FMT_ld\n #pragma GCC poison TARGET_FMT_lu\n \n-#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS\n-\n #pragma GCC poison CONFIG_ALPHA_DIS\n #pragma GCC poison CONFIG_HPPA_DIS\n #pragma GCC poison CONFIG_I386_DIS\ndiff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h\nindex a799f42db3..e04bfeee12 100644\n--- a/target/alpha/cpu-param.h\n+++ b/target/alpha/cpu-param.h\n@@ -8,9 +8,6 @@\n #ifndef ALPHA_CPU_PARAM_H\n #define ALPHA_CPU_PARAM_H\n \n-/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */\n-#define TARGET_PHYS_ADDR_SPACE_BITS 44\n-\n #ifdef CONFIG_USER_ONLY\n /*\n * Allow user-only to vary page size. Real hardware allows only 8k and 64k,\ndiff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h\nindex 8b46c7c570..08785125ad 100644\n--- a/target/arm/cpu-param.h\n+++ b/target/arm/cpu-param.h\n@@ -9,10 +9,8 @@\n #define ARM_CPU_PARAM_H\n \n #ifdef TARGET_AARCH64\n-# define TARGET_PHYS_ADDR_SPACE_BITS 52\n # define TARGET_VIRT_ADDR_SPACE_BITS 52\n #else\n-# define TARGET_PHYS_ADDR_SPACE_BITS 40\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \ndiff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h\nindex f74bfc2580..066ada1e9c 100644\n--- a/target/avr/cpu-param.h\n+++ b/target/avr/cpu-param.h\n@@ -22,7 +22,6 @@\n #define AVR_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 10\n-#define TARGET_PHYS_ADDR_SPACE_BITS 24\n #define TARGET_VIRT_ADDR_SPACE_BITS 24\n \n #define TARGET_INSN_START_EXTRA_WORDS 0\ndiff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h\nindex 635d509e74..31da1a239f 100644\n--- a/target/hexagon/cpu-param.h\n+++ b/target/hexagon/cpu-param.h\n@@ -20,7 +20,6 @@\n \n #define TARGET_PAGE_BITS 16 /* 64K pages */\n \n-#define TARGET_PHYS_ADDR_SPACE_BITS 36\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n #define TARGET_INSN_START_EXTRA_WORDS 0\ndiff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h\nindex 9bf7ac76d0..3a874c29ee 100644\n--- a/target/hppa/cpu-param.h\n+++ b/target/hppa/cpu-param.h\n@@ -9,11 +9,8 @@\n #define HPPA_CPU_PARAM_H\n \n #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32)\n-# define TARGET_PHYS_ADDR_SPACE_BITS 32\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #else\n-/* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */\n-# define TARGET_PHYS_ADDR_SPACE_BITS 40\n # define TARGET_VIRT_ADDR_SPACE_BITS 64\n #endif\n \ndiff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h\nindex ebb844bcc8..9e4cb74e04 100644\n--- a/target/i386/cpu-param.h\n+++ b/target/i386/cpu-param.h\n@@ -9,7 +9,6 @@\n #define I386_CPU_PARAM_H\n \n #ifdef TARGET_X86_64\n-# define TARGET_PHYS_ADDR_SPACE_BITS 52\n /*\n * ??? This is really 48 bits, sign-extended, but the only thing\n * accessible to userland with bit 48 set is the VSYSCALL, and that\n@@ -17,7 +16,6 @@\n */\n # define TARGET_VIRT_ADDR_SPACE_BITS 47\n #else\n-# define TARGET_PHYS_ADDR_SPACE_BITS 36\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n #define TARGET_PAGE_BITS 12\ndiff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h\nindex 58cc45a377..7779461054 100644\n--- a/target/loongarch/cpu-param.h\n+++ b/target/loongarch/cpu-param.h\n@@ -8,7 +8,6 @@\n #ifndef LOONGARCH_CPU_PARAM_H\n #define LOONGARCH_CPU_PARAM_H\n \n-#define TARGET_PHYS_ADDR_SPACE_BITS 48\n #define TARGET_VIRT_ADDR_SPACE_BITS 48\n \n #define TARGET_PAGE_BITS 12\ndiff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h\nindex 256a2b5f8b..802d8fc674 100644\n--- a/target/m68k/cpu-param.h\n+++ b/target/m68k/cpu-param.h\n@@ -14,7 +14,6 @@\n * use the smallest one\n */\n #define TARGET_PAGE_BITS 12\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n #define TARGET_INSN_START_EXTRA_WORDS 1\ndiff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h\nindex e0a3794513..90a0cf2435 100644\n--- a/target/microblaze/cpu-param.h\n+++ b/target/microblaze/cpu-param.h\n@@ -17,10 +17,8 @@\n * of address space.\n */\n #ifdef CONFIG_USER_ONLY\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n #else\n-#define TARGET_PHYS_ADDR_SPACE_BITS 64\n #define TARGET_VIRT_ADDR_SPACE_BITS 64\n #endif\n \ndiff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h\nindex 58f450827f..d62110e732 100644\n--- a/target/mips/cpu-param.h\n+++ b/target/mips/cpu-param.h\n@@ -8,10 +8,8 @@\n #define MIPS_CPU_PARAM_H\n \n #ifdef TARGET_ABI_MIPSN64\n-#define TARGET_PHYS_ADDR_SPACE_BITS 48\n #define TARGET_VIRT_ADDR_SPACE_BITS 48\n #else\n-#define TARGET_PHYS_ADDR_SPACE_BITS 40\n # ifdef CONFIG_USER_ONLY\n # define TARGET_VIRT_ADDR_SPACE_BITS 31\n # else\ndiff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h\nindex b4f57bbe69..740cf76ddd 100644\n--- a/target/openrisc/cpu-param.h\n+++ b/target/openrisc/cpu-param.h\n@@ -9,7 +9,6 @@\n #define OPENRISC_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 13\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n #define TARGET_INSN_START_EXTRA_WORDS 1\ndiff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h\nindex e4ed9080ee..2065915dc5 100644\n--- a/target/ppc/cpu-param.h\n+++ b/target/ppc/cpu-param.h\n@@ -9,12 +9,6 @@\n #define PPC_CPU_PARAM_H\n \n #ifdef TARGET_PPC64\n-/*\n- * Note that the official physical address space bits is 62-M where M\n- * is implementation dependent. I've not looked up M for the set of\n- * cpus we emulate at the system level.\n- */\n-#define TARGET_PHYS_ADDR_SPACE_BITS 62\n /*\n * Note that the PPC environment architecture talks about 80 bit virtual\n * addresses, with segmentation. Obviously that's not all visible to a\n@@ -26,7 +20,6 @@\n # define TARGET_VIRT_ADDR_SPACE_BITS 64\n # endif\n #else\n-# define TARGET_PHYS_ADDR_SPACE_BITS 36\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \ndiff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h\nindex cfdc67c258..b96e1ce12e 100644\n--- a/target/riscv/cpu-param.h\n+++ b/target/riscv/cpu-param.h\n@@ -9,10 +9,8 @@\n #define RISCV_CPU_PARAM_H\n \n #if defined(TARGET_RISCV64)\n-# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */\n # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */\n #elif defined(TARGET_RISCV32)\n-# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */\n # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */\n #endif\n #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */\ndiff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h\nindex 84934f3bca..4cf6183aa0 100644\n--- a/target/rx/cpu-param.h\n+++ b/target/rx/cpu-param.h\n@@ -21,7 +21,6 @@\n \n #define TARGET_PAGE_BITS 12\n \n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n #define TARGET_INSN_START_EXTRA_WORDS 0\ndiff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h\nindex abfae3bedf..e46e0757c6 100644\n--- a/target/s390x/cpu-param.h\n+++ b/target/s390x/cpu-param.h\n@@ -9,7 +9,6 @@\n #define S390_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 12\n-#define TARGET_PHYS_ADDR_SPACE_BITS 64\n #define TARGET_VIRT_ADDR_SPACE_BITS 64\n \n #define TARGET_INSN_START_EXTRA_WORDS 2\ndiff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h\nindex f328715ee8..e2632bb20f 100644\n--- a/target/sh4/cpu-param.h\n+++ b/target/sh4/cpu-param.h\n@@ -9,7 +9,6 @@\n #define SH4_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 12 /* 4k */\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #ifdef CONFIG_USER_ONLY\n # define TARGET_VIRT_ADDR_SPACE_BITS 31\n #else\ndiff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h\nindex 45eea9d6ba..4c92862ea3 100644\n--- a/target/sparc/cpu-param.h\n+++ b/target/sparc/cpu-param.h\n@@ -9,7 +9,6 @@\n \n #ifdef TARGET_SPARC64\n # define TARGET_PAGE_BITS 13 /* 8k */\n-# define TARGET_PHYS_ADDR_SPACE_BITS 41\n # ifdef TARGET_ABI32\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n # else\n@@ -17,7 +16,6 @@\n # endif\n #else\n # define TARGET_PAGE_BITS 12 /* 4k */\n-# define TARGET_PHYS_ADDR_SPACE_BITS 36\n # define TARGET_VIRT_ADDR_SPACE_BITS 32\n #endif\n \ndiff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h\nindex eb33a67c41..f260a888c2 100644\n--- a/target/tricore/cpu-param.h\n+++ b/target/tricore/cpu-param.h\n@@ -9,7 +9,6 @@\n #define TRICORE_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 14\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \n #define TARGET_INSN_START_EXTRA_WORDS 0\ndiff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h\nindex 7a0c22c900..328176281e 100644\n--- a/target/xtensa/cpu-param.h\n+++ b/target/xtensa/cpu-param.h\n@@ -9,7 +9,6 @@\n #define XTENSA_CPU_PARAM_H\n \n #define TARGET_PAGE_BITS 12\n-#define TARGET_PHYS_ADDR_SPACE_BITS 32\n #ifdef CONFIG_USER_ONLY\n #define TARGET_VIRT_ADDR_SPACE_BITS 30\n #else\n", "prefixes": [ "v4", "8/8" ] }