Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2194997/?format=api
{ "id": 2194997, "url": "http://patchwork.ozlabs.org/api/patches/2194997/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210-phys_addr-v4-5-725a589e83c8@rev.ng/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210-phys_addr-v4-5-725a589e83c8@rev.ng>", "list_archive_url": null, "date": "2026-02-10T11:33:16", "name": "[v4,5/8] target/loongarch: Introduce loongarch_palen_mask()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "96e9004fc358c8e197b8b6a97a2cda186f6e7ba2", "submitter": { "id": 92408, "url": "http://patchwork.ozlabs.org/api/people/92408/?format=api", "name": "Anton Johansson", "email": "anjo@rev.ng" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210-phys_addr-v4-5-725a589e83c8@rev.ng/mbox/", "series": [ { "id": 491656, "url": "http://patchwork.ozlabs.org/api/series/491656/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491656", "date": "2026-02-10T11:33:12", "name": "single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/491656/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194997/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194997/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=rev.ng header.i=@rev.ng header.a=rsa-sha256\n header.s=dkim header.b=OZAVLzbD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f9KCC6pBdz1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 22:31:35 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vplx0-0005Oh-Eo; Tue, 10 Feb 2026 06:30:38 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vplwt-0005ML-3I\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:31 -0500", "from rev.ng ([94.130.142.21])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vplwr-0008KQ-9A\n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:30 -0500" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng;\n s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:\n Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID:\n Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe:\n List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post:\n List-Help; bh=Z80TN9jbZwmUXaaLMZy0r2yPGv1D70SCG1gJo7mX+Gk=; b=OZAVLzbDprh6p1p\n BYqButiHmG9XUxg2Grz/yohxXnuiV/LCwlO4TKcR1vswnQhgdugQQAEnJFec3j1iW/rvFeJ8ig07C\n AiCocQyMUbKiYk5LergMV+nCNw1d6sw0HwprRRBn6eNx0Ms1k2kcUPKfmY6rVkXSkQJt7bVymWl1X\n iI=;", "Date": "Tue, 10 Feb 2026 12:33:16 +0100", "Subject": "[PATCH v4 5/8] target/loongarch: Introduce loongarch_palen_mask()", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260210-phys_addr-v4-5-725a589e83c8@rev.ng>", "References": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>", "In-Reply-To": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>,\n Anton Johansson <anjo@rev.ng>, palmer@dabbelt.com, alistair.francis@wdc.com,\n pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn,\n deller@gmx.de", "Received-SPF": "pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng;\n helo=rev.ng", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001,\n T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Anton Johansson <anjo@rev.ng>", "From": "Anton Johansson via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, define a\nruntime function to construct a mask from the PALEN cpucfg field.\nThe mask is then used when converting from virtual to physical\naddresses.\n\nSigned-off-by: Anton Johansson <anjo@rev.ng>\n---\n target/loongarch/cpu-mmu.h | 1 +\n target/loongarch/internals.h | 1 -\n target/loongarch/cpu_helper.c | 14 +++++++++++---\n target/loongarch/tcg/tlb_helper.c | 12 ++++++++----\n 4 files changed, 20 insertions(+), 8 deletions(-)", "diff": "diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h\nindex 2259de9d36..3286accc14 100644\n--- a/target/loongarch/cpu-mmu.h\n+++ b/target/loongarch/cpu-mmu.h\n@@ -98,5 +98,6 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,\n void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,\n uint64_t *dir_width, unsigned int level);\n hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n+uint64_t loongarch_palen_mask(CPULoongArchState *env);\n \n #endif /* LOONGARCH_CPU_MMU_H */\ndiff --git a/target/loongarch/internals.h b/target/loongarch/internals.h\nindex 8793bd9df6..e01dbed40f 100644\n--- a/target/loongarch/internals.h\n+++ b/target/loongarch/internals.h\n@@ -13,7 +13,6 @@\n #define FCMP_UN 0b0100 /* unordered */\n #define FCMP_GT 0b1000 /* fp0 > fp1 */\n \n-#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)\n #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)\n \n void loongarch_translate_init(void);\ndiff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c\nindex 51ad9ff2b4..c94361ba17 100644\n--- a/target/loongarch/cpu_helper.c\n+++ b/target/loongarch/cpu_helper.c\n@@ -147,6 +147,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,\n {\n CPUState *cs = env_cpu(env);\n hwaddr index = 0, phys = 0;\n+ uint64_t palen_mask = loongarch_palen_mask(env);\n uint64_t dir_base, dir_width;\n uint64_t base, pte;\n int level;\n@@ -154,13 +155,14 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,\n TLBRet ret;\n MemTxResult ret1;\n \n+\n address = context->addr;\n if ((address >> 63) & 0x1) {\n base = env->CSR_PGDH;\n } else {\n base = env->CSR_PGDL;\n }\n- base &= TARGET_PHYS_MASK;\n+ base &= palen_mask;\n \n for (level = 4; level >= 0; level--) {\n get_dir_base_width(env, &dir_base, &dir_width, level);\n@@ -181,7 +183,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,\n break;\n } else {\n /* Discard high bits with page directory table */\n- base &= TARGET_PHYS_MASK;\n+ base &= palen_mask;\n }\n }\n }\n@@ -315,7 +317,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,\n /* Check PG and DA */\n address = context->addr;\n if (da & !pg) {\n- context->physical = address & TARGET_PHYS_MASK;\n+ context->physical = address & loongarch_palen_mask(env);\n context->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n context->mmu_index = MMU_DA_IDX;\n return TLBRET_MATCH;\n@@ -364,3 +366,9 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)\n }\n return context.physical;\n }\n+\n+uint64_t loongarch_palen_mask(CPULoongArchState *env)\n+{\n+ uint64_t phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN);\n+ return MAKE_64BIT_MASK(0, phys_bits);\n+}\ndiff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c\nindex b6e9a3a3c7..c1dc77a8f8 100644\n--- a/target/loongarch/tcg/tlb_helper.c\n+++ b/target/loongarch/tcg/tlb_helper.c\n@@ -692,8 +692,10 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,\n CPUState *cs = env_cpu(env);\n uint64_t badvaddr;\n hwaddr index, phys;\n+ uint64_t palen_mask = loongarch_palen_mask(env);\n uint64_t dir_base, dir_width;\n \n+\n if (unlikely((level == 0) || (level > 4))) {\n qemu_log_mask(LOG_GUEST_ERROR,\n \"Attepted LDDIR with level %u\\n\", level);\n@@ -715,11 +717,11 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,\n }\n \n badvaddr = env->CSR_TLBRBADV;\n- base = base & TARGET_PHYS_MASK;\n+ base = base & palen_mask;\n get_dir_base_width(env, &dir_base, &dir_width, level);\n index = (badvaddr >> dir_base) & ((1 << dir_width) - 1);\n phys = base | index << 3;\n- return ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK;\n+ return ldq_le_phys(cs->as, phys) & palen_mask;\n }\n \n void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,\n@@ -730,9 +732,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,\n uint64_t badv;\n uint64_t ptbase = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE);\n uint64_t ptwidth = FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH);\n+ uint64_t palen_mask = loongarch_palen_mask(env);\n uint64_t dir_base, dir_width;\n uint8_t ps;\n \n+\n /*\n * The parameter \"base\" has only two types,\n * one is the page table base address,\n@@ -740,7 +744,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,\n * and the other is the huge page entry,\n * whose bit 6 should be 1.\n */\n- base = base & TARGET_PHYS_MASK;\n+ base = base & palen_mask;\n if (FIELD_EX64(base, TLBENTRY, HUGE)) {\n /*\n * Gets the huge page level and Gets huge page size.\n@@ -781,7 +785,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong odd,\n ptoffset0 = ptindex << 3;\n ptoffset1 = (ptindex + 1) << 3;\n phys = base | (odd ? ptoffset1 : ptoffset0);\n- tmp0 = ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK;\n+ tmp0 = ldq_le_phys(cs->as, phys) & palen_mask;\n ps = ptbase;\n }\n \n", "prefixes": [ "v4", "5/8" ] }