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GET /api/patches/2194957/?format=api
{ "id": 2194957, "url": "http://patchwork.ozlabs.org/api/patches/2194957/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260210094044.72591-8-ganboing@gmail.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260210094044.72591-8-ganboing@gmail.com>", "list_archive_url": null, "date": "2026-02-10T09:40:44", "name": "[7/7,NOT-FOR-UPSTREAM] Test program for misaligned load/store", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6087d8290f90acbad10c6bd92d9125338ffe7997", "submitter": { "id": 86401, "url": "http://patchwork.ozlabs.org/api/people/86401/?format=api", "name": "Bo Gan", "email": "ganboing@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260210094044.72591-8-ganboing@gmail.com/mbox/", "series": [ { "id": 491635, "url": "http://patchwork.ozlabs.org/api/series/491635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=491635", "date": "2026-02-10T09:40:41", "name": "Fixes for load/store misaligned and access faults", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491635/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194957/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194957/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=h6xdyOyV;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=UxkQDyVt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: Build: gcc -o test-misaligned-ldst test-misaligned-ldst.c\n ldst.S Failure observed before the fix on QEMU with 64-bit Linux and 32-bit\n test ... loadfp 64, insn cfldsp, n=64, off=1, cmp=788796a5b4c3d2e1 loadfp\n 64, insn cfldsp, n=64, off=2, cmp=69788796a5b4c3d2 loadfp 64, insn cfldsp,\n n=64, off=3, cmp=5a69788796a5b4c3 loadfp 64, insn cfldsp [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:52c listed in]\n [list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n provider\n [ganboing(at)gmail.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Build: gcc -o test-misaligned-ldst test-misaligned-ldst.c ldst.S\n\nFailure observed before the fix on QEMU with 64-bit Linux and 32-bit test\n\n...\nloadfp 64, insn cfldsp, n=64, off=1, cmp=788796a5b4c3d2e1\nloadfp 64, insn cfldsp, n=64, off=2, cmp=69788796a5b4c3d2\nloadfp 64, insn cfldsp, n=64, off=3, cmp=5a69788796a5b4c3\nloadfp 64, insn cfldsp, n=64, off=4, cmp=4b5a69788796a5b4\nloadfp 64, insn cfldsp, n=64, off=5, cmp=3c4b5a69788796a5\nloadfp 64, insn cfldsp, n=64, off=6, cmp=2d3c4b5a69788796\nloadfp 64, insn cfldsp, n=64, off=7, cmp=1e2d3c4b5a697887\nloadfp 32, insn cflw, n=32, off=1, cmp=ffffffffb4c3d2e1\n./test32: failed at load_f 1 4 0: 0\n\nWith the patch series:\n\n...\nloadfp 64, insn cfldsp, n=64, off=1, cmp=788796a5b4c3d2e1\nloadfp 64, insn cfldsp, n=64, off=2, cmp=69788796a5b4c3d2\nloadfp 64, insn cfldsp, n=64, off=3, cmp=5a69788796a5b4c3\nloadfp 64, insn cfldsp, n=64, off=4, cmp=4b5a69788796a5b4\nloadfp 64, insn cfldsp, n=64, off=5, cmp=3c4b5a69788796a5\nloadfp 64, insn cfldsp, n=64, off=6, cmp=2d3c4b5a69788796\nloadfp 64, insn cfldsp, n=64, off=7, cmp=1e2d3c4b5a697887\nloadfp 32, insn cflw, n=32, off=1, cmp=ffffffffb4c3d2e1\nloadfp 32, insn cflw, n=32, off=2, cmp=ffffffffa5b4c3d2\nloadfp 32, insn cflw, n=32, off=3, cmp=ffffffff96a5b4c3\nloadfp 32, insn cflw, n=32, off=5, cmp=ffffffff788796a5\nloadfp 32, insn cflw, n=32, off=6, cmp=ffffffff69788796\nloadfp 32, insn cflw, n=32, off=7, cmp=ffffffff5a697887\nloadfp 32, insn cflw, n=32, off=9, cmp=ffffffff3c4b5a69\nloadfp 32, insn cflw, n=32, off=10, cmp=ffffffff2d3c4b5a\nloadfp 32, insn cflw, n=32, off=11, cmp=ffffffff1e2d3c4b\nloadfp 32, insn cflwsp, n=64, off=1, cmp=ffffffffb4c3d2e1\nloadfp 32, insn cflwsp, n=64, off=2, cmp=ffffffffa5b4c3d2\nloadfp 32, insn cflwsp, n=64, off=3, cmp=ffffffff96a5b4c3\nloadfp 32, insn cflwsp, n=64, off=5, cmp=ffffffff788796a5\nloadfp 32, insn cflwsp, n=64, off=6, cmp=ffffffff69788796\nloadfp 32, insn cflwsp, n=64, off=7, cmp=ffffffff5a697887\nloadfp 32, insn cflwsp, n=64, off=9, cmp=ffffffff3c4b5a69\nloadfp 32, insn cflwsp, n=64, off=10, cmp=ffffffff2d3c4b5a\nloadfp 32, insn cflwsp, n=64, off=11, cmp=ffffffff1e2d3c4b\n\n<no failure>\n---\n tests/ldst.S | 134 +++++++++++++++++++++++++++\n tests/ldst.h | 170 +++++++++++++++++++++++++++++++++++\n tests/test-misaligned-ldst.c | 154 +++++++++++++++++++++++++++++++\n 3 files changed, 458 insertions(+)\n create mode 100644 tests/ldst.S\n create mode 100644 tests/ldst.h\n create mode 100644 tests/test-misaligned-ldst.c", "diff": "diff --git a/tests/ldst.S b/tests/ldst.S\nnew file mode 100644\nindex 00000000..66f88e42\n--- /dev/null\n+++ b/tests/ldst.S\n@@ -0,0 +1,134 @@\n+.altmacro\n+\n+.macro mem_repeat name:req, ldst:req, op:req, rx:req, ry:req, len:req, signext=0, step=1, n=4096, max=2048\n+.globl mem_\\name\n+.type mem_\\name, @function\n+mem_\\name\\():\n+.set i, 0\n+.rept \\n\n+.set j, \\max - \\n * \\step + i * \\step\n+1:\n+\tmem_\\ldst \\op \\rx \\ry j\n+\tret\n+.ifne . - mem_\\name - (. - 1b) * (i + 1)\n+.error \"mem_\\name is not aligned\"\n+.endif\n+.set i, i + 1\n+.endr\n+.size mem_\\name, . - mem_\\name\n+\n+.align 3\n+.globl mem_\\name\\()_desc\n+.type mem_\\name\\()_desc @object\n+mem_\\name\\()_desc:\n+\t.byte \\len, \\signext, \\step, (. - mem_\\name) / \\n\n+\t.half \\max - \\n * \\step, \\n\n+#if __riscv_xlen == 32\n+\t.word mem_\\name\n+#elif __riscv_xlen == 64\n+\t.dword mem_\\name\n+#endif\n+.size mem_\\name\\()_desc, . - mem_\\name\\()_desc\n+.endm\n+\n+.macro mem_load op rs rd imm\n+\tmv \\rs, a0\n+\t\\op \\rd, \\imm(\\rs)\n+\tmv a0, \\rd\n+.endm\n+\n+.macro mem_fpld op rs rd imm\n+\tmv \\rs, a0\n+\t\\op \\rd, \\imm(\\rs)\n+\tfmv.d fa0, \\rd\n+.endm\n+\n+.macro mem_store op rs1 rs2 imm\n+\tmv \\rs2, a1\n+\tmv \\rs1, a0\n+\t\\op \\rs2, \\imm(\\rs1)\n+.endm\n+\n+.macro mem_fpst op rs1 rs2 imm\n+\tfmv.d \\rs2, fa0\n+\tmv \\rs1, a0\n+\t\\op \\rs2, \\imm(\\rs1)\n+.endm\n+\n+.macro mem_ldsp op tmp rd imm\n+\tmv \\tmp, sp\n+\tmv sp, a0\n+\t\\op \\rd, \\imm(sp)\n+\tmv sp, \\tmp\n+\tmv a0, \\rd\n+.endm\n+\n+.macro mem_fpldsp op tmp rd imm\n+\tmv \\tmp, sp\n+\tmv sp, a0\n+\t\\op \\rd, \\imm(sp)\n+\tmv sp, \\tmp\n+\tfmv.d fa0, \\rd\n+.endm\n+\n+.macro mem_stsp op tmp rs2 imm\n+\tmv \\tmp, sp\n+\tmv sp, a0\n+\tmv \\rs2, a1\n+\t\\op \\rs2, \\imm(sp)\n+\tmv sp, \\tmp\n+.endm\n+\n+.macro mem_fpstsp op tmp rs2 imm\n+\tmv \\tmp, sp\n+\tmv sp, a0\n+\tfmv.d \\rs2, fa0\n+\t\\op \\rs2, \\imm(sp)\n+\tmv sp, \\tmp\n+.endm\n+\n+mem_repeat lb load lb t0 a1 1 1\n+mem_repeat lbu load lbu t1 a2 1\n+mem_repeat sb store sb t2 a3 1\n+mem_repeat lh load lh t4 a5 2 1\n+mem_repeat lhu load lhu t5 a6 2\n+mem_repeat sh store sh t6 a7 2\n+mem_repeat lw load lw a7 t6 4 1\n+#if __riscv_xlen == 64\n+mem_repeat lwu load lwu a6 t5 4\n+#endif\n+mem_repeat sw store sw a5 t4 4\n+#if __riscv_xlen == 64\n+mem_repeat ld load ld a4 t3 8 1\n+mem_repeat sd store sd a3 t2 8\n+#endif\n+mem_repeat flw fpld flw t3 ft8 4\n+mem_repeat fsw fpst fsw t4 ft9 4\n+mem_repeat fld fpld fld t5 ft10 8\n+mem_repeat fsd fpst fsd t6 ft11 8\n+#ifdef __riscv_zcb\n+mem_repeat clbu load c.lbu a5 a1 1 0 1 4 4\n+mem_repeat csb store c.sb a4 a2 1 0 1 4 4\n+mem_repeat clh load c.lh a3 a3 2 1 2 2 4\n+mem_repeat clhu load c.lhu a2 a4 2 0 2 2 4\n+mem_repeat csh store c.sh a1 a5 2 0 2 2 4\n+#endif\n+mem_repeat clw load c.lw a5 a1 4 1 4 32 128\n+mem_repeat csw store c.sw a4 a2 4 0 4 32 128\n+mem_repeat clwsp ldsp lw t0 t6 4 1 4 64 256\n+mem_repeat cswsp stsp sw t1 t5 4 0 4 64 256\n+mem_repeat cfld fpld c.fld a3 fa2 8 0 8 32 256\n+mem_repeat cfsd fpst c.fsd a2 fa3 8 0 8 32 256\n+mem_repeat cfldsp fpldsp fld t2 ft10 8 0 8 64 512\n+mem_repeat cfsdsp fpstsp fsd t3 ft11 8 0 8 64 512\n+#if __riscv_xlen == 32\n+mem_repeat cflw fpld c.flw a5 fa4 4 0 4 32 128\n+mem_repeat cfsw fpst c.fsw a4 fa5 4 0 4 32 128\n+mem_repeat cflwsp fpldsp flw t3 ft11 4 0 4 64 256\n+mem_repeat cfswsp fpstsp fsw t4 ft10 4 0 4 64 256\n+#elif __riscv_xlen == 64\n+mem_repeat cld load c.ld a5 a4 8 1 8 32 256\n+mem_repeat csd store c.sd a4 a5 8 0 8 32 256\n+mem_repeat cldsp ldsp ld t3 t6 8 1 8 64 512\n+mem_repeat csdsp stsp sd t4 t5 8 0 8 64 512\n+#endif\ndiff --git a/tests/ldst.h b/tests/ldst.h\nnew file mode 100644\nindex 00000000..3d4b6062\n--- /dev/null\n+++ b/tests/ldst.h\n@@ -0,0 +1,170 @@\n+#include <inttypes.h>\n+\n+typedef struct {\n+\tuint8_t len;\n+\tuint8_t signext;\n+\tuint8_t imm_step;\n+\tuint8_t isize;\n+\tint16_t imm_base;\n+\tuint16_t n;\n+\tvoid *fp;\n+} mem_op_desc;\n+\n+typedef union {\n+\tunsigned long u_long;\n+\tlong i_long;\n+\tuint32_t u32[2];\n+\tint32_t i32[2];\n+\tuint64_t u64;\n+\tint64_t i64;\n+\tfloat f32[2];\n+\tdouble f64;\n+\tuint8_t bytes[8];\n+} ldst_val;\n+\n+extern mem_op_desc mem_lb_desc;\n+extern mem_op_desc mem_lbu_desc;\n+extern mem_op_desc mem_sb_desc;\n+extern mem_op_desc mem_lh_desc;\n+extern mem_op_desc mem_lhu_desc;\n+extern mem_op_desc mem_sh_desc;\n+extern mem_op_desc mem_lw_desc;\n+extern mem_op_desc mem_lwu_desc;\n+extern mem_op_desc mem_sw_desc;\n+extern mem_op_desc mem_ld_desc;\n+extern mem_op_desc mem_sd_desc;\n+extern mem_op_desc mem_flw_desc;\n+extern mem_op_desc mem_fsw_desc;\n+extern mem_op_desc mem_fld_desc;\n+extern mem_op_desc mem_fsd_desc;\n+extern mem_op_desc mem_clbu_desc;\n+extern mem_op_desc mem_csb_desc;\n+extern mem_op_desc mem_clh_desc;\n+extern mem_op_desc mem_clhu_desc;\n+extern mem_op_desc mem_csh_desc;\n+extern mem_op_desc mem_clw_desc;\n+extern mem_op_desc mem_csw_desc;\n+extern mem_op_desc mem_clwsp_desc;\n+extern mem_op_desc mem_cswsp_desc;\n+extern mem_op_desc mem_cfld_desc;\n+extern mem_op_desc mem_cfsd_desc;\n+extern mem_op_desc mem_cfldsp_desc;\n+extern mem_op_desc mem_cfsdsp_desc;\n+extern mem_op_desc mem_cflw_desc;\n+extern mem_op_desc mem_cfsw_desc;\n+extern mem_op_desc mem_cflwsp_desc;\n+extern mem_op_desc mem_cfswsp_desc;\n+extern mem_op_desc mem_cld_desc;\n+extern mem_op_desc mem_csd_desc;\n+extern mem_op_desc mem_cldsp_desc;\n+extern mem_op_desc mem_csdsp_desc;\n+\n+typedef struct ldst_func {\n+\tconst char *name;\n+\tconst mem_op_desc *desc;\n+} ldst_func;\n+\n+#define DEF_LDST_FUNC(x) { #x, &mem_ ## x ## _desc }\n+\n+static const ldst_func load_funcs[] = {\n+\tDEF_LDST_FUNC(lb),\n+\tDEF_LDST_FUNC(lbu),\n+\tDEF_LDST_FUNC(lh),\n+\tDEF_LDST_FUNC(lhu),\n+\tDEF_LDST_FUNC(lw),\n+#ifdef __riscv_zcb\n+\tDEF_LDST_FUNC(clbu),\n+\tDEF_LDST_FUNC(clh),\n+\tDEF_LDST_FUNC(clhu),\n+#endif\n+\tDEF_LDST_FUNC(clw),\n+\tDEF_LDST_FUNC(clwsp),\n+#if __riscv_xlen == 64\n+\tDEF_LDST_FUNC(lwu),\n+\tDEF_LDST_FUNC(ld),\n+\tDEF_LDST_FUNC(cld),\n+\tDEF_LDST_FUNC(cldsp),\n+#endif\n+};\n+\n+static const ldst_func store_funcs[] = {\n+\tDEF_LDST_FUNC(sb),\n+\tDEF_LDST_FUNC(sh),\n+\tDEF_LDST_FUNC(sw),\n+#ifdef __riscv_zcb\n+\tDEF_LDST_FUNC(csb),\n+\tDEF_LDST_FUNC(csh),\n+#endif\n+\tDEF_LDST_FUNC(csw),\n+\tDEF_LDST_FUNC(cswsp),\n+#if __riscv_xlen == 64\n+\tDEF_LDST_FUNC(sd),\n+\tDEF_LDST_FUNC(csd),\n+\tDEF_LDST_FUNC(csdsp),\n+#endif\n+};\n+\n+static const ldst_func loadfp_funcs[] = {\n+#if __riscv_xlen == 32\n+\tDEF_LDST_FUNC(cflw),\n+\tDEF_LDST_FUNC(cflwsp),\n+#endif\n+\tDEF_LDST_FUNC(flw),\n+\tDEF_LDST_FUNC(fld),\n+\tDEF_LDST_FUNC(cfld),\n+\tDEF_LDST_FUNC(cfldsp),\n+};\n+\n+static const ldst_func storefp_funcs[] = {\n+#if __riscv_xlen == 32\n+\tDEF_LDST_FUNC(cfsw),\n+\tDEF_LDST_FUNC(cfswsp),\n+#endif\n+\tDEF_LDST_FUNC(fsw),\n+\tDEF_LDST_FUNC(fsd),\n+\tDEF_LDST_FUNC(cfsd),\n+\tDEF_LDST_FUNC(cfsdsp),\n+};\n+\n+static inline unsigned long load_i(const void *p, unsigned func, unsigned sel)\n+{\n+\ttypedef unsigned long (*func_i)(const void *p);\n+\tconst mem_op_desc *desc = load_funcs[func].desc;\n+\n+\tlong imm = (long)desc->imm_base + desc->imm_step * sel;\n+\tfunc_i f = desc->fp + desc->isize * sel;\n+\n+\treturn f(p - imm);\n+}\n+\n+static inline void store_i(void *p, unsigned long val, unsigned func, unsigned sel)\n+{\n+\ttypedef void (*func_i)(void *p, unsigned long val);\n+\tconst mem_op_desc *desc = store_funcs[func].desc;\n+\n+\tlong imm = (long)desc->imm_base + desc->imm_step * sel;\n+\tfunc_i f = desc->fp + desc->isize * sel;\n+\tf(p - imm, val);\n+}\n+\n+static inline double load_f(const void *p, unsigned func, unsigned sel)\n+{\n+\ttypedef double (*func_f)(const void *p);\n+\tconst mem_op_desc *desc = loadfp_funcs[func].desc;\n+\n+\tlong imm = (long)desc->imm_base + desc->imm_step * sel;\n+\tfunc_f f = desc->fp + desc->isize * sel;\n+\n+\treturn f(p - imm);\n+}\n+\n+static inline void store_f(void *p, double val, unsigned func, unsigned sel)\n+{\n+\ttypedef void (*func_f)(void *p, double val);\n+\tconst mem_op_desc *desc = storefp_funcs[func].desc;\n+\n+\tlong imm = (long)desc->imm_base + desc->imm_step * sel;\n+\tfunc_f f = desc->fp + desc->isize * sel;\n+\n+\tf(p - imm, val);\n+}\ndiff --git a/tests/test-misaligned-ldst.c b/tests/test-misaligned-ldst.c\nnew file mode 100644\nindex 00000000..ccbd0d36\n--- /dev/null\n+++ b/tests/test-misaligned-ldst.c\n@@ -0,0 +1,154 @@\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdint.h>\n+#include <error.h>\n+#include \"ldst.h\"\n+\n+#define ARR_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))\n+\n+static const uint8_t patt[16] = {\n+\t0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87,\n+\t0x78, 0x69, 0x5a, 0x4b, 0x3c, 0x2d, 0x1e, 0x0f,\n+};\n+\n+static const uint64_t load_val[16] = {\n+\t0x8796a5b4c3d2e1f0ULL,\n+\t0x788796a5b4c3d2e1ULL,\n+\t0x69788796a5b4c3d2ULL,\n+\t0x5a69788796a5b4c3ULL,\n+\t0x4b5a69788796a5b4ULL,\n+\t0x3c4b5a69788796a5ULL,\n+\t0x2d3c4b5a69788796ULL,\n+\t0x1e2d3c4b5a697887ULL,\n+\t0x0f1e2d3c4b5a6978ULL,\n+\t 0x0f1e2d3c4b5a69ULL,\n+\t 0x0f1e2d3c4b5aULL,\n+\t 0x0f1e2d3c4bULL,\n+\t 0x0f1e2d3cULL,\n+\t 0x0f1e2dULL,\n+\t 0x0f1eULL,\n+\t 0x0fULL,\n+};\n+\n+int main()\n+{\n+\tunsigned i, j, k;\n+\t//ldst_val val;\n+\n+\t// Test int read\n+\tfor (j = 0; j < ARR_SIZE(load_funcs); ++j) {\n+\t\tconst mem_op_desc *desc = load_funcs[j].desc;\n+\t\tunsigned shift = 8 * (sizeof(long) - desc->len);\n+\n+\t\tfor (i = 0; i < ARR_SIZE(patt) - desc->len; ++i) {\n+\t\t\tunsigned long expected;\n+\t\t\tif (desc->len != 1 && i % desc->len == 0)\n+\t\t\t\tcontinue;\n+\n+\t\t\texpected = load_val[i];\n+\t\t\tif (desc->signext)\n+\t\t\t\texpected = (long)(expected << shift) >> shift;\n+\t\t\telse\n+\t\t\t\texpected = (expected << shift) >> shift;\n+\n+\t\t\tprintf(\"load %c%u, insn %s, n=%u, off=%u, cmp=%lx\\n\",\n+\t\t\t\tdesc->signext ? 'i' : 'u',\n+\t\t\t\tdesc->len * 8, load_funcs[j].name, desc->n, i, expected);\n+\t\t\tfflush(stdout);\n+\t\t\tfor (k = 0; k < desc->n; ++k) {\n+\t\t\t\tunsigned long read = load_i(&patt[i], j, k);\n+\t\t\t\tif (read != expected)\n+\t\t\t\t\terror(1, 0, \"failed at load_i %u %u %u: %lx\",\n+\t\t\t\t\t\ti, j, k, read);\n+\t\t\t}\n+\t\t}\n+\t}\n+\t// Test fp load\n+\tfor (j = 0; j < ARR_SIZE(loadfp_funcs); ++j) {\n+\t\tconst mem_op_desc *desc = loadfp_funcs[j].desc;\n+\n+\t\tfor (i = 0; i < ARR_SIZE(patt) - desc->len; ++i) {\n+\t\t\tldst_val expected, read;\n+\n+\t\t\texpected.u64 = load_val[i];\n+\t\t\tif (desc->len == 4) // float\n+\t\t\t\texpected.i32[1] = -1;\n+\n+\t\t\tif (i % desc->len == 0)\n+\t\t\t\tcontinue;\n+\n+\t\t\tprintf(\"loadfp %u, insn %s, n=%u, off=%u, cmp=%\" PRIx64 \"\\n\",\n+\t\t\t\tdesc->len * 8, loadfp_funcs[j].name, desc->n, i, expected.u64);\n+\t\t\tfflush(stdout);\n+\t\t\tfor (k = 0; k < desc->n; ++k) {\n+\t\t\t\tread.f64 = load_f(&patt[i], j, k);\n+\t\t\t\tif (read.u64 != expected.u64)\n+\t\t\t\t\terror(1, 0, \"failed at load_f %u %u %u: %\" PRIx64,\n+\t\t\t\t\t\ti, j, k, read.u64);\n+\t\t\t}\n+\t\t}\n+\t}\n+\t// Test int store\n+\tfor (j = 0; j < ARR_SIZE(store_funcs); ++j) {\n+\t\tconst mem_op_desc *desc = store_funcs[j].desc;\n+\n+\t\tfor (i = 0; i < ARR_SIZE(patt) - desc->len; ++i) {\n+#pragma GCC diagnostic push\n+#pragma GCC diagnostic ignored \"-Woverflow\"\n+\t\t\tldst_val val = { 0x8899aabbccddeeffULL };\n+#pragma GCC diagnostic pop\n+\t\t\tunsigned end = i + desc->len;\n+\n+\t\t\tif (desc->len != 1 && i % desc->len == 0)\n+\t\t\t\tcontinue;\n+\n+\t\t\tmemcpy(val.bytes, &patt[i], desc->len);\n+\t\t\tprintf(\"store %u, insn %s, n=%u, off=%u, src=%lx\\n\",\n+\t\t\t\tdesc->len * 8, store_funcs[j].name, desc->n, i, val.u_long);\n+\t\t\tfflush(stdout);\n+\n+\t\t\tfor (k = 0; k < desc->n; ++k) {\n+\t\t\t\tuint8_t buff[ARR_SIZE(patt)] = {};\n+\n+\t\t\t\tmemcpy(buff, patt, i);\n+\t\t\t\tmemcpy(&buff[end], &patt[end], ARR_SIZE(patt) - end);\n+\t\t\t\tstore_i(&buff[i], val.u_long, j, k);\n+\t\t\t\tif (memcmp(buff, patt, sizeof(buff)))\n+\t\t\t\t\terror(1, 0, \"faild at store_i %u %u %u\", i, j, k);\n+\t\t\t}\n+\n+\t\t}\n+\t}\n+\t// Test fp store\n+\tfor (j = 0; j < ARR_SIZE(storefp_funcs); ++j) {\n+\t\tconst mem_op_desc *desc = storefp_funcs[j].desc;\n+\n+\t\tfor (i = 0; i < ARR_SIZE(patt) - desc->len; ++i) {\n+\t\t\tldst_val val;\n+\t\t\tunsigned end = i + desc->len;\n+\n+\t\t\tval.u32[0] = 0xccddeeffUL;\n+\t\t\tval.u32[1] = 0x8899aabbUL;\n+\n+\t\t\tif (i % desc->len == 0)\n+\t\t\t\tcontinue;\n+\n+\t\t\tmemcpy(val.bytes, &patt[i], desc->len);\n+\t\t\tprintf(\"storefp %u, insn %s, n=%u, off=%u, src=%\" PRIx64 \"\\n\",\n+\t\t\t\tdesc->len * 8, storefp_funcs[j].name, desc->n, i, val.u64);\n+\t\t\tfflush(stdout);\n+\n+\t\t\tfor (k = 0; k < desc->n; ++k) {\n+\t\t\t\tuint8_t buff[ARR_SIZE(patt)] = {};\n+\n+\t\t\t\tmemcpy(buff, patt, i);\n+\t\t\t\tmemcpy(&buff[end], &patt[end], ARR_SIZE(patt) - end);\n+\t\t\t\tstore_f(&buff[i], val.f64, j, k);\n+\t\t\t\tif (memcmp(buff, patt, sizeof(buff)))\n+\t\t\t\t\terror(1, 0, \"faild at store_f %u %u %u\", i, j, k);\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n", "prefixes": [ "7/7", "NOT-FOR-UPSTREAM" ] }