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GET /api/patches/2194953/?format=api
{ "id": 2194953, "url": "http://patchwork.ozlabs.org/api/patches/2194953/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260210094044.72591-6-ganboing@gmail.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260210094044.72591-6-ganboing@gmail.com>", "list_archive_url": null, "date": "2026-02-10T09:40:42", "name": "[5/7] lib: sbi: Do not override emulator callback for vector load/store", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f07930d67d6f6b23dd4139632a862fd29a0945c4", "submitter": { "id": 86401, "url": "http://patchwork.ozlabs.org/api/people/86401/?format=api", "name": "Bo Gan", "email": "ganboing@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260210094044.72591-6-ganboing@gmail.com/mbox/", "series": [ { "id": 491635, "url": "http://patchwork.ozlabs.org/api/series/491635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=491635", "date": "2026-02-10T09:40:41", "name": "Fixes for load/store misaligned and access faults", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491635/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194953/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=WKUtLUqC;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=aQjxJw4A;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: It's wrong to override the emulator callback in\n sbi_trap_emulate_load/\n store. The function must respect the callback function passed in the\n parameter.\n Hence, let the misaligned emulator callback decid [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2607:f8b0:4864:20:0:0:0:62e listed in]\n [list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n provider\n [ganboing(at)gmail.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "It's wrong to override the emulator callback in sbi_trap_emulate_load/\nstore. The function must respect the callback function passed in the\nparameter. Hence, let the misaligned emulator callback decide when to\nuse sbi_misaligned_v_ld/st_emulator. To clean up things, also make the\nfollowing changes:\n\n- Add the `insn` parameter to the callback. The trapping insn could\n have been fetched by the caller already, thus it saves some time\n in the callback. Also the `tcntx` is added, in case the callback\n needs richer information to properly handle the trap. Specifically,\n the callback can utilize the tinst if it knows how to decode custom\n values.\n\n- Clarify that the read/write length (rlen/wlen) can be 0, in which\n case it could be a vector load/store or some customized instruction.\n The callback is responsible to handle it by parsing the insn (and\n fetch it if not available), and act accordingly.\n\nAlso fixes the following issue in the sbi_misaligned_v_ld/st_emulator\n\na. Not checking if sbi_get_insn has faulted\nb. Need to redirect the trap when OPENSBI_CC_SUPPORT_VECTOR is not\n available.\n\nFixes: c2acc5e5b0d8 (\"lib: sbi_misaligned_ldst: Add handling of vector load/store\")\nSigned-off-by: Bo Gan <ganboing@gmail.com>\n---\n include/sbi/sbi_platform.h | 92 ++++++++++++++++++++----------\n include/sbi/sbi_trap_ldst.h | 4 +-\n lib/sbi/sbi_trap_ldst.c | 111 ++++++++++++++++++++++++------------\n lib/sbi/sbi_trap_v_ldst.c | 25 ++++----\n 4 files changed, 150 insertions(+), 82 deletions(-)", "diff": "diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h\nindex e65d9877..d3b2f9ad 100644\n--- a/include/sbi/sbi_platform.h\n+++ b/include/sbi/sbi_platform.h\n@@ -137,11 +137,14 @@ struct sbi_platform_operations {\n \t\t\t\t struct sbi_ecall_return *out);\n \n \t/** platform specific handler to fixup load fault */\n-\tint (*emulate_load)(int rlen, unsigned long addr,\n-\t\t\t union sbi_ldst_data *out_val);\n+\tint (*emulate_load)(ulong insn, int rlen, ulong addr,\n+\t\t\t union sbi_ldst_data *out_val,\n+\t\t\t struct sbi_trap_context *tcntx);\n+\n \t/** platform specific handler to fixup store fault */\n-\tint (*emulate_store)(int wlen, unsigned long addr,\n-\t\t\t union sbi_ldst_data in_val);\n+\tint (*emulate_store)(ulong insn, int wlen, ulong addr,\n+\t\t\t union sbi_ldst_data in_val,\n+\t\t\t struct sbi_trap_context *tcntx);\n \n \t/** platform specific pmp setup on current HART */\n \tvoid (*pmp_set)(unsigned int n, unsigned long flags,\n@@ -612,45 +615,74 @@ static inline int sbi_platform_vendor_ext_provider(\n }\n \n /**\n- * Ask platform to emulate the trapped load\n- *\n- * @param plat pointer to struct sbi_platform\n- * @param rlen length of the load: 1/2/4/8...\n- * @param addr virtual address of the load. Platform needs to page-walk and\n- * find the physical address if necessary\n- * @param out_val value loaded\n- *\n- * @return 0 on success and negative error code on failure\n+ * Ask platform to emulate the trapped load:\n+ *\n+ * @param insn the instruction that caused the load fault (optional)\n+ * If 0, it's not fetched by caller, and the emulator can\n+ * fetch it on a need basis.\n+ * @param rlen read length in [0, 1, 2, 4, 8]. If 0, it's a special load.\n+ * In that case, it could be a vector load or customized insn,\n+ * which may read/gather a block of memory. The emulator should\n+ * further parse the @insn (fetch if 0), and act accordingly.\n+ * @param raddr read address. If @rlen is not 0, it's the base address of\n+ * the load. It doesn't necessarily match tcntx->trap->tval,\n+ * in case of unaligned load triggering access fault.\n+ * If @rlen is 0, @raddr should be ignored.\n+ * @param out_val the buffer to hold data loaded by the emulator.\n+ * If @rlen == 0, @out_val is ignored by caller.\n+ * @param tcntx trap context saved on load fault entry.\n+ *\n+ * @return >0 success: register will be updated by caller if @rlen != 0,\n+ * and mepc will be advanced by caller.\n+ * 0 success: no register modification; no mepc advancement.\n+ * <0 failure\n+ *\n+ * It's expected that if @rlen != 0, and the emulator returns >0, the\n+ * caller will set the corresponding registers with @out_val to simplify\n+ * things. Otherwise, no register manipulation is done by the caller.\n */\n static inline int sbi_platform_emulate_load(const struct sbi_platform *plat,\n-\t\t\t\t\t int rlen, unsigned long addr,\n-\t\t\t\t\t union sbi_ldst_data *out_val)\n+\t\t\t\t\t ulong insn, int rlen, ulong raddr,\n+\t\t\t\t\t union sbi_ldst_data *out_val,\n+\t\t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tif (plat && sbi_platform_ops(plat)->emulate_load) {\n-\t\treturn sbi_platform_ops(plat)->emulate_load(rlen, addr,\n-\t\t\t\t\t\t\t out_val);\n+\t\treturn sbi_platform_ops(plat)->emulate_load(insn, rlen, raddr,\n+\t\t\t\t\t\t\t out_val, tcntx);\n \t}\n \treturn SBI_ENOTSUPP;\n }\n \n /**\n- * Ask platform to emulate the trapped store\n- *\n- * @param plat pointer to struct sbi_platform\n- * @param wlen length of the store: 1/2/4/8...\n- * @param addr virtual address of the store. Platform needs to page-walk and\n- * find the physical address if necessary\n- * @param in_val value to store\n- *\n- * @return 0 on success and negative error code on failure\n+ * Ask platform to emulate the trapped store:\n+ *\n+ * @param insn the instruction that caused the store fault (optional).\n+ * If 0, it's not fetched by caller, and the emulator can\n+ * fetch it on a need basis.\n+ * @param wlen write length in [0, 1, 2, 4, 8]. If 0, it's a special store.\n+ * In that case, it could be a vector store or customized insn,\n+ * which may write/scatter a block of memory. The emulator should\n+ * further parse the @insn (fetch if 0), and act accordingly.\n+ * @param waddr write address. If @wlen is not 0, it's the base address of\n+ * the store. It doesn't necessarily match tcntx->trap->tval,\n+ * in case of unaligned store triggering access fault.\n+ * If @wlen is 0, @waddr should be ignored.\n+ * @param in_val the buffer to hold data about to be stored by the emulator.\n+ * If @wlen == 0, @in_val should be ignored.\n+ * @param tcntx trap context saved on store fault entry.\n+ *\n+ * @return >0 success: mepc will be advanced by caller.\n+ * 0 success: no mepc advancement.\n+ * <0 failure\n */\n static inline int sbi_platform_emulate_store(const struct sbi_platform *plat,\n-\t\t\t\t\t int wlen, unsigned long addr,\n-\t\t\t\t\t union sbi_ldst_data in_val)\n+\t\t\t\t\t ulong insn, int wlen, ulong waddr,\n+\t\t\t\t\t union sbi_ldst_data in_val,\n+\t\t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tif (plat && sbi_platform_ops(plat)->emulate_store) {\n-\t\treturn sbi_platform_ops(plat)->emulate_store(wlen, addr,\n-\t\t\t\t\t\t\t in_val);\n+\t\treturn sbi_platform_ops(plat)->emulate_store(insn, wlen, waddr,\n+\t\t\t\t\t\t\t in_val, tcntx);\n \t}\n \treturn SBI_ENOTSUPP;\n }\ndiff --git a/include/sbi/sbi_trap_ldst.h b/include/sbi/sbi_trap_ldst.h\nindex a6a6c75b..33c348c5 100644\n--- a/include/sbi/sbi_trap_ldst.h\n+++ b/include/sbi/sbi_trap_ldst.h\n@@ -31,10 +31,10 @@ int sbi_store_access_handler(struct sbi_trap_context *tcntx);\n ulong sbi_misaligned_tinst_fixup(ulong orig_tinst, ulong new_tinst,\n \t\t\t\t ulong addr_offset);\n \n-int sbi_misaligned_v_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n+int sbi_misaligned_v_ld_emulator(ulong insn,\n \t\t\t\t struct sbi_trap_context *tcntx);\n \n-int sbi_misaligned_v_st_emulator(int wlen, union sbi_ldst_data in_val,\n+int sbi_misaligned_v_st_emulator(ulong insn,\n \t\t\t\t struct sbi_trap_context *tcntx);\n \n #endif\ndiff --git a/lib/sbi/sbi_trap_ldst.c b/lib/sbi/sbi_trap_ldst.c\nindex 448406b1..22c4d5a7 100644\n--- a/lib/sbi/sbi_trap_ldst.c\n+++ b/lib/sbi/sbi_trap_ldst.c\n@@ -18,18 +18,18 @@\n \n /**\n * Load emulator callback:\n- *\n- * @return rlen=success, 0=success w/o regs modification, or negative error\n+ * Refer to comments of `sbi_platform_emulate_load`.\n */\n-typedef int (*sbi_trap_ld_emulator)(int rlen, union sbi_ldst_data *out_val,\n+typedef int (*sbi_trap_ld_emulator)(ulong insn, int rlen, ulong raddr,\n+\t\t\t\t union sbi_ldst_data *out_val,\n \t\t\t\t struct sbi_trap_context *tcntx);\n \n /**\n * Store emulator callback:\n- *\n- * @return wlen=success, 0=success w/o regs modification, or negative error\n+ * Refer to comments of `sbi_platform_emulate_store`.\n */\n-typedef int (*sbi_trap_st_emulator)(int wlen, union sbi_ldst_data in_val,\n+typedef int (*sbi_trap_st_emulator)(ulong insn, int wlen, ulong waddr,\n+\t\t\t\t union sbi_ldst_data in_val,\n \t\t\t\t struct sbi_trap_context *tcntx);\n \n ulong sbi_misaligned_tinst_fixup(ulong orig_tinst, ulong new_tinst,\n@@ -52,13 +52,15 @@ static int sbi_trap_emulate_load(struct sbi_trap_context *tcntx,\n \tulong insn, insn_len;\n \tunion sbi_ldst_data val = { 0 };\n \tstruct sbi_trap_info uptrap;\n-\tint rc, fp = 0, shift = 0, len = 0, vector = 0;\n+\tint rc, fp = 0, shift = 0, len = 0;\n+\tbool xform = false;\n \n \tif (orig_trap->tinst & 0x1) {\n \t\t/*\n \t\t * Bit[0] == 1 implies trapped instruction value is\n \t\t * transformed instruction or custom instruction.\n \t\t */\n+\t\txform\t = true;\n \t\tinsn\t = orig_trap->tinst | INSN_16BIT_MASK;\n \t\tinsn_len = (orig_trap->tinst & 0x2) ? INSN_LEN(insn) : 2;\n \t} else {\n@@ -144,27 +146,20 @@ static int sbi_trap_emulate_load(struct sbi_trap_context *tcntx,\n \t\tlen = 2;\n \t\tshift = 8 * (sizeof(ulong) - len);\n \t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if (IS_VECTOR_LOAD_STORE(insn)) {\n-\t\tvector = 1;\n-\t\temu = sbi_misaligned_v_ld_emulator;\n-\t} else {\n-\t\treturn sbi_trap_redirect(regs, orig_trap);\n \t}\n \n-\trc = emu(len, &val, tcntx);\n+\trc = emu(xform ? 0 : insn, len, orig_trap->tval, &val, tcntx);\n \tif (rc <= 0)\n \t\treturn rc;\n \n-\tif (!vector) {\n-\t\tif (!fp)\n-\t\t\tSET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift);\n+\tif (!fp)\n+\t\tSET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift);\n #ifdef __riscv_flen\n-\t\telse if (len == 8)\n-\t\t\tSET_F64_RD(insn, regs, val.data_u64);\n-\t\telse\n-\t\t\tSET_F32_RD(insn, regs, val.data_ulong);\n+\telse if (len == 8)\n+\t\tSET_F64_RD(insn, regs, val.data_u64);\n+\telse\n+\t\tSET_F32_RD(insn, regs, val.data_ulong);\n #endif\n-\t}\n \n \tregs->mepc += insn_len;\n \n@@ -180,12 +175,14 @@ static int sbi_trap_emulate_store(struct sbi_trap_context *tcntx,\n \tunion sbi_ldst_data val;\n \tstruct sbi_trap_info uptrap;\n \tint rc, len = 0;\n+\tbool xform = false;\n \n \tif (orig_trap->tinst & 0x1) {\n \t\t/*\n \t\t * Bit[0] == 1 implies trapped instruction value is\n \t\t * transformed instruction or custom instruction.\n \t\t */\n+\t\txform\t = true;\n \t\tinsn\t = orig_trap->tinst | INSN_16BIT_MASK;\n \t\tinsn_len = (orig_trap->tinst & 0x2) ? INSN_LEN(insn) : 2;\n \t} else {\n@@ -253,13 +250,9 @@ static int sbi_trap_emulate_store(struct sbi_trap_context *tcntx,\n \t} else if ((insn & INSN_MASK_C_SH) == INSN_MATCH_C_SH) {\n \t\tlen\t\t= 2;\n \t\tval.data_ulong = GET_RS2S(insn, regs);\n-\t} else if (IS_VECTOR_LOAD_STORE(insn)) {\n-\t\temu = sbi_misaligned_v_st_emulator;\n-\t} else {\n-\t\treturn sbi_trap_redirect(regs, orig_trap);\n \t}\n \n-\trc = emu(len, val, tcntx);\n+\trc = emu(xform ? 0 : insn, len, orig_trap->tval, val, tcntx);\n \tif (rc <= 0)\n \t\treturn rc;\n \n@@ -268,7 +261,8 @@ static int sbi_trap_emulate_store(struct sbi_trap_context *tcntx,\n \treturn 0;\n }\n \n-static int sbi_misaligned_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n+static int sbi_misaligned_ld_emulator(ulong insn, int rlen, ulong addr,\n+\t\t\t\t union sbi_ldst_data *out_val,\n \t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n@@ -276,9 +270,25 @@ static int sbi_misaligned_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n \tstruct sbi_trap_info uptrap;\n \tint i;\n \n+\tif (!rlen) {\n+\t\tif (!insn) {\n+\t\t\tinsn = sbi_get_insn(regs->mepc, &uptrap);\n+\t\t\tif (uptrap.cause)\n+\t\t\t\treturn sbi_trap_redirect(regs, &uptrap);\n+\t\t}\n+\t\tif (IS_VECTOR_LOAD_STORE(insn))\n+\t\t\treturn sbi_misaligned_v_ld_emulator(insn, tcntx);\n+\t\telse\n+\t\t\t/* Unrecognized instruction. Can't emulate it. */\n+\t\t\treturn sbi_trap_redirect(regs, orig_trap);\n+\t}\n+\t/* For misaligned fault, addr must be the same as orig_trap->tval */\n+\tif (addr != orig_trap->tval)\n+\t\treturn SBI_EFAIL;\n+\n \tfor (i = 0; i < rlen; i++) {\n \t\tout_val->data_bytes[i] =\n-\t\t\tsbi_load_u8((void *)(orig_trap->tval + i), &uptrap);\n+\t\t\tsbi_load_u8((void *)(addr + i), &uptrap);\n \t\tif (uptrap.cause) {\n \t\t\tuptrap.tinst = sbi_misaligned_tinst_fixup(\n \t\t\t\torig_trap->tinst, uptrap.tinst, i);\n@@ -293,7 +303,8 @@ int sbi_misaligned_load_handler(struct sbi_trap_context *tcntx)\n \treturn sbi_trap_emulate_load(tcntx, sbi_misaligned_ld_emulator);\n }\n \n-static int sbi_misaligned_st_emulator(int wlen, union sbi_ldst_data in_val,\n+static int sbi_misaligned_st_emulator(ulong insn, int wlen, ulong addr,\n+\t\t\t\t union sbi_ldst_data in_val,\n \t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n@@ -301,8 +312,24 @@ static int sbi_misaligned_st_emulator(int wlen, union sbi_ldst_data in_val,\n \tstruct sbi_trap_info uptrap;\n \tint i;\n \n+\tif (!wlen) {\n+\t\tif (!insn) {\n+\t\t\tinsn = sbi_get_insn(regs->mepc, &uptrap);\n+\t\t\tif (uptrap.cause)\n+\t\t\t\treturn sbi_trap_redirect(regs, &uptrap);\n+\t\t}\n+\t\tif (IS_VECTOR_LOAD_STORE(insn))\n+\t\t\treturn sbi_misaligned_v_st_emulator(insn, tcntx);\n+\t\telse\n+\t\t\t/* Unrecognized instruction. Can't emulate it. */\n+\t\t\treturn sbi_trap_redirect(regs, orig_trap);\n+\t}\n+\t/* For misaligned fault, addr must be the same as orig_trap->tval */\n+\tif (addr != orig_trap->tval)\n+\t\treturn SBI_EFAIL;\n+\n \tfor (i = 0; i < wlen; i++) {\n-\t\tsbi_store_u8((void *)(orig_trap->tval + i),\n+\t\tsbi_store_u8((void *)(addr + i),\n \t\t\t in_val.data_bytes[i], &uptrap);\n \t\tif (uptrap.cause) {\n \t\t\tuptrap.tinst = sbi_misaligned_tinst_fixup(\n@@ -318,22 +345,26 @@ int sbi_misaligned_store_handler(struct sbi_trap_context *tcntx)\n \treturn sbi_trap_emulate_store(tcntx, sbi_misaligned_st_emulator);\n }\n \n-static int sbi_ld_access_emulator(int rlen, union sbi_ldst_data *out_val,\n+static int sbi_ld_access_emulator(ulong insn, int rlen, ulong addr,\n+\t\t\t\t union sbi_ldst_data *out_val,\n \t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n \tstruct sbi_trap_regs *regs = &tcntx->regs;\n+\tint rc;\n \n \t/* If fault came from M mode, just fail */\n \tif (sbi_mstatus_prev_mode(regs->mstatus) == PRV_M)\n \t\treturn SBI_EINVAL;\n \n+\trc = sbi_platform_emulate_load(sbi_platform_thishart_ptr(),\n+\t\t\t\t insn, rlen, addr, out_val, tcntx);\n+\n \t/* If platform emulator failed, we redirect instead of fail */\n-\tif (sbi_platform_emulate_load(sbi_platform_thishart_ptr(), rlen,\n-\t\t\t\t orig_trap->tval, out_val))\n+\tif (rc < 0)\n \t\treturn sbi_trap_redirect(regs, orig_trap);\n \n-\treturn rlen;\n+\treturn rc;\n }\n \n int sbi_load_access_handler(struct sbi_trap_context *tcntx)\n@@ -341,22 +372,26 @@ int sbi_load_access_handler(struct sbi_trap_context *tcntx)\n \treturn sbi_trap_emulate_load(tcntx, sbi_ld_access_emulator);\n }\n \n-static int sbi_st_access_emulator(int wlen, union sbi_ldst_data in_val,\n+static int sbi_st_access_emulator(ulong insn, int wlen, ulong addr,\n+\t\t\t\t union sbi_ldst_data in_val,\n \t\t\t\t struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n \tstruct sbi_trap_regs *regs = &tcntx->regs;\n+\tint rc;\n \n \t/* If fault came from M mode, just fail */\n \tif (sbi_mstatus_prev_mode(regs->mstatus) == PRV_M)\n \t\treturn SBI_EINVAL;\n \n+\trc = sbi_platform_emulate_store(sbi_platform_thishart_ptr(),\n+\t\t\t\t\tinsn, wlen, addr, in_val, tcntx);\n+\n \t/* If platform emulator failed, we redirect instead of fail */\n-\tif (sbi_platform_emulate_store(sbi_platform_thishart_ptr(), wlen,\n-\t\t\t\t orig_trap->tval, in_val))\n+\tif (rc < 0)\n \t\treturn sbi_trap_redirect(regs, orig_trap);\n \n-\treturn wlen;\n+\treturn rc;\n }\n \n int sbi_store_access_handler(struct sbi_trap_context *tcntx)\ndiff --git a/lib/sbi/sbi_trap_v_ldst.c b/lib/sbi/sbi_trap_v_ldst.c\nindex f4d469dc..f361ce04 100644\n--- a/lib/sbi/sbi_trap_v_ldst.c\n+++ b/lib/sbi/sbi_trap_v_ldst.c\n@@ -137,13 +137,11 @@ static inline void vsetvl(ulong vl, ulong vtype)\n \t\t\t:: \"r\" (vl), \"r\" (vtype));\n }\n \n-int sbi_misaligned_v_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n-\t\t\t\t struct sbi_trap_context *tcntx)\n+int sbi_misaligned_v_ld_emulator(ulong insn, struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n \tstruct sbi_trap_regs *regs = &tcntx->regs;\n \tstruct sbi_trap_info uptrap;\n-\tulong insn = sbi_get_insn(regs->mepc, &uptrap);\n \tulong vl = csr_read(CSR_VL);\n \tulong vtype = csr_read(CSR_VTYPE);\n \tulong vlenb = csr_read(CSR_VLENB);\n@@ -237,13 +235,11 @@ int sbi_misaligned_v_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n \treturn vl;\n }\n \n-int sbi_misaligned_v_st_emulator(int wlen, union sbi_ldst_data in_val,\n-\t\t\t\t struct sbi_trap_context *tcntx)\n+int sbi_misaligned_v_st_emulator(ulong insn, struct sbi_trap_context *tcntx)\n {\n \tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n \tstruct sbi_trap_regs *regs = &tcntx->regs;\n \tstruct sbi_trap_info uptrap;\n-\tulong insn = sbi_get_insn(regs->mepc, &uptrap);\n \tulong vl = csr_read(CSR_VL);\n \tulong vtype = csr_read(CSR_VTYPE);\n \tulong vlenb = csr_read(CSR_VLENB);\n@@ -331,14 +327,19 @@ int sbi_misaligned_v_st_emulator(int wlen, union sbi_ldst_data in_val,\n \treturn vl;\n }\n #else\n-int sbi_misaligned_v_ld_emulator(int rlen, union sbi_ldst_data *out_val,\n-\t\t\t\t struct sbi_trap_context *tcntx)\n+int sbi_misaligned_v_ld_emulator(ulong insn, struct sbi_trap_context *tcntx)\n {\n-\treturn 0;\n+\tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n+\tstruct sbi_trap_regs *regs = &tcntx->regs;\n+\n+\treturn sbi_trap_redirect(regs, orig_trap);\n }\n-int sbi_misaligned_v_st_emulator(int wlen, union sbi_ldst_data in_val,\n-\t\t\t\t struct sbi_trap_context *tcntx)\n+\n+int sbi_misaligned_v_st_emulator(ulong insn, struct sbi_trap_context *tcntx)\n {\n-\treturn 0;\n+\tconst struct sbi_trap_info *orig_trap = &tcntx->trap;\n+\tstruct sbi_trap_regs *regs = &tcntx->regs;\n+\n+\treturn sbi_trap_redirect(regs, orig_trap);\n }\n #endif /* OPENSBI_CC_SUPPORT_VECTOR */\n", "prefixes": [ "5/7" ] }