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GET /api/patches/2194936/?format=api
{ "id": 2194936, "url": "http://patchwork.ozlabs.org/api/patches/2194936/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-10-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210091018.1553489-10-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-02-10T09:10:32", "name": "[v5,09/21] hw/i3c/dw-i3c: Add register RO field masks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4fdad4b6b0ab8795dd582e7e7707eb838e34f273", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-10-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 491625, "url": "http://patchwork.ozlabs.org/api/series/491625/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491625", "date": "2026-02-10T09:10:19", "name": "i3c: aspeed: Add I3C support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491625/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194936/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194936/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=flp7K/Bk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 10 Feb 2026 04:10:51 -0500", "from TYPPR06MB8206.apcprd06.prod.outlook.com (2603:1096:405:383::19)\n by KUZPR06MB8268.apcprd06.prod.outlook.com (2603:1096:d10:62::15)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9587.19; Tue, 10 Feb\n 2026 09:10:32 +0000", "from TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3]) by TYPPR06MB8206.apcprd06.prod.outlook.com\n ([fe80::e659:1ead:77cb:f6d3%3]) with mapi id 15.20.9587.017; Tue, 10 Feb 2026\n 09:10:32 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=mXVH4zlH1mb6soh/jYcyA27/TlIE5ztgePCtkwhFk0+JUFIO1kagiENsfOLSk9Hk8d2o915wfJHIIcXHOItwNLWCGLWMaBudlppSw8E2ZaIJLPBCoLT1oaTPJEy/Ypx84iGf1pptkUSndddPrRJspLLcelkhzs2xhexE5EnKOSVfYRA52Gv0lYGglTmy77Ui5X9LUSeewvw0boQ1pah0DR+3hnPiv7m9GaCdFpiwel+S6MfDgGND1nKTF1ohJcq7X9X0oPHN1Uv/izHg5Wo8wQM4/5Rm71TvGRbh/Yz7yVCvtyvibX+jVPd8rOxH9oEeiqbnSN2fvnPaLdDQdmc+ZA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=R/AYuRkWP6BeUepikGanog70cRJ8IwLDIUKHi20W3No=;\n b=UsP57w/PfAm3sheq55YuWrZ1zMk1cIBS/7YgMOcyp8W2Kz98lxi0Htu/Zkl/TWKzb6NcP/Jo6ZuERlmhP/c03jgDw1ET2Pk6ulvq6uLAkDEqsRFsxyCBN+bCF+oyCAufbJ0SufL7a9WtJetygIeb93X1cDlnbhp8buyQBMlggmYAc4qLNyY+khbDaL00uFQFUlVC5+Rj7kz1pUkFwNP0PCMUjicOh2Q1AHcxTOpnmlEZjqDK36U/lyQrUSnz6jthoh60Dxrz0EmdHz7YSDa8LnlHVaaBKS+xNJ9cTEZMO6aNto+uh90I1Iccf8HGLvZFRYNDal5C/LIeQ5JARp2z7A==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=R/AYuRkWP6BeUepikGanog70cRJ8IwLDIUKHi20W3No=;\n b=flp7K/BkuAlWQ2XP3nY393NzJR01z/fWODNGdd5K3HrsfPVBzV1Kew8WyfYxjV12hgrg79eefMxsWVIxjp8rH7DIIJ/AVZqBL4ULfGxPkoz1HJii/MJym5GeWfVtqcmtn9bn741be4Ez86ei3/kwzENhH2b0dPaJuvdFOP2PsjAHrt1tTTbnzCYHGMRHdC7NaeTePvLA4MD/YhCLW6wDlSu5nOx5/UxfTJP4qAGUbRTURZoDcL5XfKmZl3PflW06E6fo1kyYYj1aUzeB2PMJqVZc9/dQlLdG0ZUgPuuB7wPlHwrO1xiaqbEdPVRj+D2iaPxrn9qUqcshyIrB0/keTg==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n\t=?iso-8859-1?q?Marc-Andr=E9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?iso-8859-1?q?Daniel_P=2E_Berrang=E9?= <berrange@redhat.com>,\n\t=?iso-8859-1?q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:ARM TCG CPUs\" <qemu-arm@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n Kane Chen <kane_chen@aspeedtech.com>, \"nabihestefan@google.com\"\n <nabihestefan@google.com>, Joe Komlodi <komlodi@google.com>, Patrick Venture\n <venture@google.com>", "Subject": "[PATCH v5 09/21] hw/i3c/dw-i3c: Add register RO field masks", "Thread-Topic": "[PATCH v5 09/21] hw/i3c/dw-i3c: Add register RO field masks", "Thread-Index": "AQHcmm0cNdB3bq9V3EGUdM69KPICKA==", "Date": "Tue, 10 Feb 2026 09:10:32 +0000", "Message-ID": "<20260210091018.1553489-10-jamin_lin@aspeedtech.com>", "References": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=flp7K/Bk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 428e480d-67fa-4256-9ded-08de68843e8d", "X-MS-Exchange-CrossTenant-originalarrivaltime": "10 Feb 2026 09:10:32.7191 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n tPfEPLMTLHsIR8Z6+UTZfQiR5s/T+wbahwiz4jg7pO8OQ5urdlY14cNI6dmzkuQftgH+CBcWGJqu6vyocWieOrp/Osr60/1MjcMQh8XfNoY=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KUZPR06MB8268", "Received-SPF": "pass client-ip=2a01:111:f403:c40f::6;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=SEYPR02CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Adds read-only register masks for the DwC I3C controller.\n\nSigned-off-by: Joe Komlodi <komlodi@google.com>\nReviewed-by: Patrick Venture <venture@google.com>\nReviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/i3c/dw-i3c.c | 40 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 40 insertions(+)", "diff": "diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c\nindex 28da6016a1..87c8f63da9 100644\n--- a/hw/i3c/dw-i3c.c\n+++ b/hw/i3c/dw-i3c.c\n@@ -296,6 +296,45 @@ static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {\n [R_SLAVE_CONFIG] = 0x00000023,\n };\n \n+static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = {\n+ [R_DEVICE_CTRL] = 0x04fffe00,\n+ [R_DEVICE_ADDR] = 0x7f807f80,\n+ [R_HW_CAPABILITY] = 0xffffffff,\n+ [R_IBI_QUEUE_STATUS] = 0xffffffff,\n+ [R_DATA_BUFFER_THLD_CTRL] = 0xf8f8f8f8,\n+ [R_IBI_QUEUE_CTRL] = 0xfffffff0,\n+ [R_RESET_CTRL] = 0xffffffc0,\n+ [R_SLV_EVENT_CTRL] = 0xffffff3f,\n+ [R_INTR_STATUS] = 0xffff809f,\n+ [R_INTR_STATUS_EN] = 0xffff8080,\n+ [R_INTR_SIGNAL_EN] = 0xffff8080,\n+ [R_INTR_FORCE] = 0xffff8000,\n+ [R_QUEUE_STATUS_LEVEL] = 0xffffffff,\n+ [R_DATA_BUFFER_STATUS_LEVEL] = 0xffffffff,\n+ [R_PRESENT_STATE] = 0xffffffff,\n+ [R_CCC_DEVICE_STATUS] = 0xffffffff,\n+ [R_I3C_VER_ID] = 0xffffffff,\n+ [R_I3C_VER_TYPE] = 0xffffffff,\n+ [R_DEVICE_ADDR_TABLE_POINTER] = 0xffffffff,\n+ [R_DEV_CHAR_TABLE_POINTER] = 0xffcbffff,\n+ [R_SLV_PID_VALUE] = 0xffff0fff,\n+ [R_SLV_CHAR_CTRL] = 0xffffffff,\n+ [A_VENDOR_SPECIFIC_REG_POINTER] = 0xffffffff,\n+ [R_SLV_MAX_LEN] = 0xffffffff,\n+ [R_MAX_READ_TURNAROUND] = 0xffffffff,\n+ [R_MAX_DATA_SPEED] = 0xffffffff,\n+ [R_SLV_INTR_REQ] = 0xfffffff0,\n+ [R_SLV_TSX_SYMBL_TIMING] = 0xffffffc0,\n+ [R_DEVICE_CTRL_EXTENDED] = 0xfffffff8,\n+ [R_SCL_I3C_OD_TIMING] = 0xff00ff00,\n+ [R_SCL_I3C_PP_TIMING] = 0xff00ff00,\n+ [R_SCL_I2C_FMP_TIMING] = 0xff000000,\n+ [R_SCL_EXT_TERMN_LCNT_TIMING] = 0x0000fff0,\n+ [R_BUS_IDLE_TIMING] = 0xfff00000,\n+ [R_EXTENDED_CAPABILITY] = 0xffffffff,\n+ [R_SLAVE_CONFIG] = 0xffffffff,\n+};\n+\n static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)\n {\n DWI3C *s = DW_I3C(opaque);\n@@ -324,6 +363,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,\n \n trace_dw_i3c_write(s->id, offset, value);\n \n+ value &= ~dw_i3c_ro[addr];\n switch (addr) {\n case R_HW_CAPABILITY:\n case R_RESPONSE_QUEUE_PORT:\n", "prefixes": [ "v5", "09/21" ] }