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GET /api/patches/2194935/?format=api
{ "id": 2194935, "url": "http://patchwork.ozlabs.org/api/patches/2194935/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-16-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210091018.1553489-16-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-02-10T09:10:41", "name": "[v5,15/21] hw/i3c/dw-i3c: Add ctrl MMIO handling", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ccb7381cd6be92b36338388b9d38f555b06b5c55", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-16-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 491625, "url": "http://patchwork.ozlabs.org/api/series/491625/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491625", "date": "2026-02-10T09:10:19", "name": "i3c: aspeed: Add I3C support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491625/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194935/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194935/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=R5WQ0Wgu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=zmVF+Hu280YwIRW2Y2PU2OYpm86SrAuPXXf0GR+tRTo=;\n b=yM1F+4VFYbgyHdJu9qQyrWTeh+f0fZUK3uL18vEMoe0nkKS00RqDQcebLsG32lY4E4itM0ona0FORkv09Mhu6n3pISb4AOYmN0Wk+olKpCkdL0/ya+JcIrx9cT+fxVKoJEBo5CMlBZgRXZweHkt2pQZ/f9FE7G6ImX+B1fM1S7Rrjl5aqn3UFaC3xN8U8VGSGTU6omUJLv9yWnHeZ8neH/plQu9k/TiKp6KfAAwbT1isornW3igKDNtU/ugDQkbfAF69Y332eWA1w+SOKLnekJpnZGw1jxIQi49jMi0AP9R8lToT69TrZwSjBq60RNmIwjaNPPr5HDYxrcVaEzkUGQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=zmVF+Hu280YwIRW2Y2PU2OYpm86SrAuPXXf0GR+tRTo=;\n b=R5WQ0Wguj6NdmtQWHwM/B4A/K9fu6aiiY6FWAigxy+NjONIoNkheM0SFyI6MUX14yHJGIcnY3KRr+9BIgiGz7+alGA3tqj8KOPI8VZKD+CGR0qOQhJcilRECMmFtVvSkzkrSHjRBlzzL5AgD1siQIzuXzi+hL1UmZy8bKwdn7kdj8htpQIgs2trPILkdHBJUwwFMwcglsuWuyQuRh+31FZOB1odqD9tSx8jlYOA6Nx0PkGKaJvQONhJt1s8ibUCWSbLXxdyl/qmuL6o4lc/HEjlkcw7C47ebFhcNp++vZduPp6AHFpYdCvZFgcuvG6FsCA52QrucpYbXae22DO64Iw==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n\t=?iso-8859-1?q?Marc-Andr=E9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?iso-8859-1?q?Daniel_P=2E_Berrang=E9?= <berrange@redhat.com>,\n\t=?iso-8859-1?q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:ARM TCG CPUs\" <qemu-arm@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n Kane Chen <kane_chen@aspeedtech.com>, \"nabihestefan@google.com\"\n <nabihestefan@google.com>, Joe Komlodi <komlodi@google.com>, Titus Rwantare\n <titusr@google.com>, Patrick Venture <venture@google.com>", "Subject": "[PATCH v5 15/21] hw/i3c/dw-i3c: Add ctrl MMIO handling", "Thread-Topic": "[PATCH v5 15/21] hw/i3c/dw-i3c: Add ctrl MMIO handling", "Thread-Index": "AQHcmm0hs+8Te5qUKkKQhXc2qeUFIg==", "Date": "Tue, 10 Feb 2026 09:10:41 +0000", "Message-ID": "<20260210091018.1553489-16-jamin_lin@aspeedtech.com>", "References": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=R5WQ0Wgu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n be24e802-1d00-48ed-b801-08de6884444d", "X-MS-Exchange-CrossTenant-originalarrivaltime": "10 Feb 2026 09:10:41.3372 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n 8bZc7beam3w+iqEWr3jusByQdyvMi5WS3PV3p3BOFNylXhiq5ENY6azugKG8/prvwjz0Q2CGLLCLZm/Ma73jUtAidUxz0kxXR6NLdFwtwCw=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KUZPR06MB8268", "Received-SPF": "pass client-ip=2a01:111:f403:c40f::6;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=SEYPR02CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Adds functionality to the CTRL register.\n\nSigned-off-by: Joe Komlodi <komlodi@google.com>\nReviewed-by: Titus Rwantare <titusr@google.com>\nReviewed-by: Patrick Venture <venture@google.com>\nReviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/i3c/dw-i3c.c | 35 +++++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)", "diff": "diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c\nindex 832fcf326a..b6ec0d9579 100644\n--- a/hw/i3c/dw-i3c.c\n+++ b/hw/i3c/dw-i3c.c\n@@ -344,6 +344,8 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] = {\n [R_SLAVE_CONFIG] = 0xffffffff,\n };\n \n+static void dw_i3c_cmd_queue_execute(DWI3C *s);\n+\n static inline bool dw_i3c_has_hdr_ts(DWI3C *s)\n {\n return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS);\n@@ -503,6 +505,36 @@ static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uint8_t *data,\n return ret;\n }\n \n+static void dw_i3c_ctrl_w(DWI3C *s, uint32_t val)\n+{\n+ /*\n+ * If the user is setting I3C_RESUME, the controller was halted.\n+ * Try and resume execution and leave the bit cleared.\n+ */\n+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) {\n+ dw_i3c_cmd_queue_execute(s);\n+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0);\n+ }\n+ /*\n+ * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is\n+ * sent.\n+ */\n+ if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) {\n+ dw_i3c_end_transfer(s, /*is_i2c=*/true);\n+ dw_i3c_end_transfer(s, /*is_i2c=*/false);\n+ val = FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0);\n+ ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1);\n+ dw_i3c_update_irq(s);\n+ }\n+ /* Update present state. */\n+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS,\n+ DW_I3C_TRANSFER_STATE_IDLE);\n+ ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS,\n+ DW_I3C_TRANSFER_STATUS_IDLE);\n+\n+ s->regs[R_DEVICE_CTRL] = val;\n+}\n+\n static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset)\n {\n /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array. */\n@@ -1575,6 +1607,9 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,\n \"] = 0x%08\" PRIx64 \"\\n\",\n __func__, offset, value);\n break;\n+ case R_DEVICE_CTRL:\n+ dw_i3c_ctrl_w(s, val32);\n+ break;\n case R_RX_TX_DATA_PORT:\n dw_i3c_push_tx(s, val32);\n break;\n", "prefixes": [ "v5", "15/21" ] }