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GET /api/patches/2194932/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2194932,
    "url": "http://patchwork.ozlabs.org/api/patches/2194932/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-17-jamin_lin@aspeedtech.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
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        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260210091018.1553489-17-jamin_lin@aspeedtech.com>",
    "list_archive_url": null,
    "date": "2026-02-10T09:10:43",
    "name": "[v5,16/21] hw/i3c/dw-i3c: Add controller resets",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "e601edb8f489767eac37b2cbd32639ca52bdfada",
    "submitter": {
        "id": 81768,
        "url": "http://patchwork.ozlabs.org/api/people/81768/?format=api",
        "name": "Jamin Lin",
        "email": "jamin_lin@aspeedtech.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-17-jamin_lin@aspeedtech.com/mbox/",
    "series": [
        {
            "id": 491625,
            "url": "http://patchwork.ozlabs.org/api/series/491625/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491625",
            "date": "2026-02-10T09:10:19",
            "name": "i3c: aspeed: Add I3C support",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/491625/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2194932/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2194932/checks/",
    "tags": {},
    "related": [],
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        "From": "Jamin Lin <jamin_lin@aspeedtech.com>",
        "To": "Paolo Bonzini <pbonzini@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n\t=?iso-8859-1?q?Marc-Andr=E9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?iso-8859-1?q?Daniel_P=2E_Berrang=E9?= <berrange@redhat.com>,\n\t=?iso-8859-1?q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n  \"open list:ARM TCG CPUs\" <qemu-arm@nongnu.org>",
        "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n Kane Chen <kane_chen@aspeedtech.com>, \"nabihestefan@google.com\"\n <nabihestefan@google.com>, Joe Komlodi <komlodi@google.com>, Patrick Venture\n <venture@google.com>, Stephen Longfield <slongfield@google.com>",
        "Subject": "[PATCH v5 16/21] hw/i3c/dw-i3c: Add controller resets",
        "Thread-Topic": "[PATCH v5 16/21] hw/i3c/dw-i3c: Add controller resets",
        "Thread-Index": "AQHcmm0iOoO98wBrVkm7uZ9FFOaTuw==",
        "Date": "Tue, 10 Feb 2026 09:10:43 +0000",
        "Message-ID": "<20260210091018.1553489-17-jamin_lin@aspeedtech.com>",
        "References": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>",
        "In-Reply-To": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>",
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    "content": "Adds behavior to the device reset register.\n\nSigned-off-by: Joe Komlodi <komlodi@google.com>\nReviewed-by: Patrick Venture <venture@google.com>\nReviewed-by: Stephen Longfield <slongfield@google.com>\nReviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/i3c/dw-i3c.c     | 117 ++++++++++++++++++++++++++++++++++++++++++++\n hw/i3c/trace-events |   1 +\n 2 files changed, 118 insertions(+)",
    "diff": "diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c\nindex b6ec0d9579..d742458129 100644\n--- a/hw/i3c/dw-i3c.c\n+++ b/hw/i3c/dw-i3c.c\n@@ -860,6 +860,122 @@ static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val)\n     dw_i3c_update_irq(s);\n }\n \n+static void dw_i3c_cmd_queue_reset(DWI3C *s)\n+{\n+    fifo32_reset(&s->cmd_queue);\n+\n+    ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC,\n+                     fifo32_num_free(&s->cmd_queue));\n+    uint8_t empty_threshold = ARRAY_FIELD_EX32(s->regs, QUEUE_THLD_CTRL,\n+                                               CMD_BUF_EMPTY_THLD);\n+    if (fifo32_num_free(&s->cmd_queue) >= empty_threshold) {\n+        ARRAY_FIELD_DP32(s->regs, INTR_STATUS, CMD_QUEUE_RDY, 1);\n+        dw_i3c_update_irq(s);\n+    };\n+}\n+\n+static void dw_i3c_resp_queue_reset(DWI3C *s)\n+{\n+    fifo32_reset(&s->resp_queue);\n+\n+    ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, RESP_BUF_BLR,\n+                     fifo32_num_used(&s->resp_queue));\n+    /*\n+     * This interrupt will always be cleared because the threshold is a minimum\n+     * of 1 and the queue size is 0.\n+     */\n+    ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RESP_RDY, 0);\n+    dw_i3c_update_irq(s);\n+}\n+\n+static void dw_i3c_ibi_queue_reset(DWI3C *s)\n+{\n+    fifo32_reset(&s->ibi_queue);\n+\n+    ARRAY_FIELD_DP32(s->regs, QUEUE_STATUS_LEVEL, IBI_BUF_BLR,\n+                     fifo32_num_used(&s->resp_queue));\n+    /*\n+     * This interrupt will always be cleared because the threshold is a minimum\n+     * of 1 and the queue size is 0.\n+     */\n+    ARRAY_FIELD_DP32(s->regs, INTR_STATUS, IBI_THLD, 0);\n+    dw_i3c_update_irq(s);\n+}\n+\n+static void dw_i3c_tx_queue_reset(DWI3C *s)\n+{\n+    fifo32_reset(&s->tx_queue);\n+\n+    ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC,\n+                     fifo32_num_free(&s->tx_queue));\n+    /* TX buf is empty, so this interrupt will always be set. */\n+    ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TX_THLD, 1);\n+    dw_i3c_update_irq(s);\n+}\n+\n+static void dw_i3c_rx_queue_reset(DWI3C *s)\n+{\n+    fifo32_reset(&s->rx_queue);\n+\n+    ARRAY_FIELD_DP32(s->regs, DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR,\n+                     fifo32_num_used(&s->resp_queue));\n+    /*\n+     * This interrupt will always be cleared because the threshold is a minimum\n+     * of 1 and the queue size is 0.\n+     */\n+    ARRAY_FIELD_DP32(s->regs, INTR_STATUS, RX_THLD, 0);\n+    dw_i3c_update_irq(s);\n+}\n+\n+static void dw_i3c_reset(DeviceState *dev)\n+{\n+    DWI3C *s = DW_I3C(dev);\n+    trace_dw_i3c_reset(s->cfg.id);\n+\n+    memcpy(s->regs, dw_i3c_resets, sizeof(s->regs));\n+    /*\n+     * The user config for these may differ from our resets array, set them\n+     * manually.\n+     */\n+    ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, ADDR,\n+                     s->cfg.dev_addr_table_pointer);\n+    ARRAY_FIELD_DP32(s->regs, DEVICE_ADDR_TABLE_POINTER, DEPTH,\n+                     s->cfg.dev_addr_table_depth);\n+    ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER,\n+                     P_DEV_CHAR_TABLE_START_ADDR,\n+                     s->cfg.dev_char_table_pointer);\n+    ARRAY_FIELD_DP32(s->regs, DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH,\n+                     s->cfg.dev_char_table_depth);\n+\n+    dw_i3c_cmd_queue_reset(s);\n+    dw_i3c_resp_queue_reset(s);\n+    dw_i3c_ibi_queue_reset(s);\n+    dw_i3c_tx_queue_reset(s);\n+    dw_i3c_rx_queue_reset(s);\n+}\n+\n+static void dw_i3c_reset_ctrl_w(DWI3C *s, uint32_t val)\n+{\n+    if (FIELD_EX32(val, RESET_CTRL, CORE_RESET)) {\n+        dw_i3c_reset(DEVICE(s));\n+    }\n+    if (FIELD_EX32(val, RESET_CTRL, CMD_QUEUE_RESET)) {\n+        dw_i3c_cmd_queue_reset(s);\n+    }\n+    if (FIELD_EX32(val, RESET_CTRL, RESP_QUEUE_RESET)) {\n+        dw_i3c_resp_queue_reset(s);\n+    }\n+    if (FIELD_EX32(val, RESET_CTRL, TX_BUF_RESET)) {\n+        dw_i3c_tx_queue_reset(s);\n+    }\n+    if (FIELD_EX32(val, RESET_CTRL, RX_BUF_RESET)) {\n+        dw_i3c_rx_queue_reset(s);\n+    }\n+    if (FIELD_EX32(val, RESET_CTRL, IBI_QUEUE_RESET)) {\n+        dw_i3c_ibi_queue_reset(s);\n+    }\n+}\n+\n static uint32_t dw_i3c_pop_rx(DWI3C *s)\n {\n     if (fifo32_is_empty(&s->rx_queue)) {\n@@ -1617,6 +1733,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, uint64_t value,\n         dw_i3c_cmd_queue_port_w(s, val32);\n         break;\n     case R_RESET_CTRL:\n+        dw_i3c_reset_ctrl_w(s, val32);\n         break;\n     case R_INTR_STATUS:\n         dw_i3c_intr_status_w(s, val32);\ndiff --git a/hw/i3c/trace-events b/hw/i3c/trace-events\nindex a262fcce39..39f33d9a50 100644\n--- a/hw/i3c/trace-events\n+++ b/hw/i3c/trace-events\n@@ -11,6 +11,7 @@ dw_i3c_send(uint32_t deviceid, uint32_t num_bytes) \"I3C Dev[%u] send %\" PRId32 \"\n dw_i3c_recv_data(uint32_t deviceid, uint32_t num_bytes) \"I3C Dev[%u] recv %\" PRId32 \" bytes from bus\"\n dw_i3c_ibi_recv(uint32_t deviceid, uint8_t ibi_byte) \"I3C Dev[%u] recv IBI byte 0x%\" PRIx8\n dw_i3c_ibi_handle(uint32_t deviceid, uint8_t addr, bool rnw) \"I3C Dev[%u] handle IBI from address 0x%\" PRIx8 \" RnW=%d\"\n+dw_i3c_reset(uint32_t deviceid) \"I3C Dev[%u] reset\"\n dw_i3c_pop_rx(uint32_t deviceid, uint32_t data) \"I3C Dev[%u] pop 0x%\" PRIx32 \" from RX FIFO\"\n dw_i3c_resp_queue_push(uint32_t deviceid, uint32_t data) \"I3C Dev[%u] push 0x%\" PRIx32 \" to response queue\"\n dw_i3c_push_tx(uint32_t deviceid, uint32_t data) \"I3C Dev[%u] push 0x%\" PRIx32 \" to TX FIFO\"\n",
    "prefixes": [
        "v5",
        "16/21"
    ]
}