Patch Detail
get:
Show a patch.
patch:
Update a patch.
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Update a patch.
GET /api/patches/2194928/?format=api
{ "id": 2194928, "url": "http://patchwork.ozlabs.org/api/patches/2194928/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-6-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210091018.1553489-6-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-02-10T09:10:27", "name": "[v5,05/21] hw/i3c/dw-i3c: Add more register fields", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "93959d5189937c2cd7d585fa8c7fdb4e8bfa9f99", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-6-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 491625, "url": "http://patchwork.ozlabs.org/api/series/491625/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491625", "date": "2026-02-10T09:10:19", "name": "i3c: aspeed: Add I3C support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491625/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194928/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194928/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com 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b=ceiHdL84dN9UVMsX8hAaSz+m4XvDy40s65XgAfzgfutFNf1W7c8EyG5Kg7xa/KeLqIMRbZCK8rB03dS31GxdIcIa7ERWND1RPmpp5qAFKZRQ/Z8WCAYODfKtYZWAQso9wh3eN9GBLd8SEelEPAoE+bKAgWnxUyR9Pmg8t84i2Jp9fJCMID/5g96Vn8gozdIXAodRY3PyT7r8D+uRnY7bgf2YKR3CzVal5wnfqQR2LJ0nIrwTiZ/Ak7MSQd3n4PrJqXRyTJX8nYrQrKgvTXLqEr3hiO3gcHQeUdqKFpzdEb8xBSmJ5/Uwd2myiwc+e0cGGgtWfzENNB2WXqiTHHJ2sQ==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n\t=?iso-8859-1?q?Marc-Andr=E9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?iso-8859-1?q?Daniel_P=2E_Berrang=E9?= <berrange@redhat.com>,\n\t=?iso-8859-1?q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:ARM TCG CPUs\" <qemu-arm@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n Kane Chen <kane_chen@aspeedtech.com>, \"nabihestefan@google.com\"\n <nabihestefan@google.com>, Joe Komlodi <komlodi@google.com>, Patrick Venture\n <venture@google.com>", "Subject": "[PATCH v5 05/21] hw/i3c/dw-i3c: Add more register fields", "Thread-Topic": "[PATCH v5 05/21] hw/i3c/dw-i3c: Add more register fields", "Thread-Index": "AQHcmm0YgPZlS9q25EqHG1SjEZnJsg==", "Date": "Tue, 10 Feb 2026 09:10:27 +0000", "Message-ID": "<20260210091018.1553489-6-jamin_lin@aspeedtech.com>", "References": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n 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helo=OS8PR02CU002.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001, UPPERCASE_75_100=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Adds the rest of the Designware register fields.\n\nSigned-off-by: Joe Komlodi <komlodi@google.com>\nReviewed-by: Patrick Venture <venture@google.com>\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n hw/i3c/dw-i3c.c | 199 ++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 199 insertions(+)", "diff": "diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c\nindex 6cadc59191..48dde008de 100644\n--- a/hw/i3c/dw-i3c.c\n+++ b/hw/i3c/dw-i3c.c\n@@ -19,54 +19,253 @@\n #include \"trace.h\"\n \n REG32(DEVICE_CTRL, 0x00)\n+ FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1)\n+ FIELD(DEVICE_CTRL, I2C_SLAVE_PRESENT, 7, 1)\n+ FIELD(DEVICE_CTRL, HOT_JOIN_ACK_NACK_CTRL, 8, 1)\n+ FIELD(DEVICE_CTRL, IDLE_CNT_MULTIPLIER, 24, 2)\n+ FIELD(DEVICE_CTRL, SLV_ADAPT_TO_I2C_I3C_MODE, 27, 1)\n+ FIELD(DEVICE_CTRL, DMA_HANDSHAKE_EN, 28, 1)\n+ FIELD(DEVICE_CTRL, I3C_ABORT, 29, 1)\n+ FIELD(DEVICE_CTRL, I3C_RESUME, 30, 1)\n+ FIELD(DEVICE_CTRL, I3C_EN, 31, 1)\n REG32(DEVICE_ADDR, 0x04)\n+ FIELD(DEVICE_ADDR, STATIC_ADDR, 0, 7)\n+ FIELD(DEVICE_ADDR, STATIC_ADDR_VALID, 15, 1)\n+ FIELD(DEVICE_ADDR, DYNAMIC_ADDR, 16, 7)\n+ FIELD(DEVICE_ADDR, DYNAMIC_ADDR_VALID, 31, 1)\n REG32(HW_CAPABILITY, 0x08)\n+ FIELD(HW_CAPABILITY, DEVICE_ROLE_CONFIG, 0, 3)\n+ FIELD(HW_CAPABILITY, HDR_DDR, 3, 1)\n+ FIELD(HW_CAPABILITY, HDR_TS, 4, 1)\n REG32(COMMAND_QUEUE_PORT, 0x0c)\n+ FIELD(COMMAND_QUEUE_PORT, CMD_ATTR, 0, 3)\n+ /* Transfer command structure */\n+ FIELD(COMMAND_QUEUE_PORT, TID, 3, 4)\n+ FIELD(COMMAND_QUEUE_PORT, CMD, 7, 8)\n+ FIELD(COMMAND_QUEUE_PORT, CP, 15, 1)\n+ FIELD(COMMAND_QUEUE_PORT, DEV_INDEX, 16, 5)\n+ FIELD(COMMAND_QUEUE_PORT, SPEED, 21, 3)\n+ FIELD(COMMAND_QUEUE_PORT, ROC, 26, 1)\n+ FIELD(COMMAND_QUEUE_PORT, SDAP, 27, 1)\n+ FIELD(COMMAND_QUEUE_PORT, RNW, 28, 1)\n+ FIELD(COMMAND_QUEUE_PORT, TOC, 30, 1)\n+ FIELD(COMMAND_QUEUE_PORT, PEC, 31, 1)\n+ /* Transfer argument data structure */\n+ FIELD(COMMAND_QUEUE_PORT, DB, 8, 8)\n+ FIELD(COMMAND_QUEUE_PORT, DL, 16, 16)\n+ /* Short data argument data structure */\n+ FIELD(COMMAND_QUEUE_PORT, BYTE_STRB, 3, 3)\n+ FIELD(COMMAND_QUEUE_PORT, BYTE0, 8, 8)\n+ FIELD(COMMAND_QUEUE_PORT, BYTE1, 16, 8)\n+ FIELD(COMMAND_QUEUE_PORT, BYTE2, 24, 8)\n+ /* Address assignment command structure */\n+ /*\n+ * bits 3..21 and 26..31 are the same as the transfer command structure, or\n+ * marked as reserved.\n+ */\n+ FIELD(COMMAND_QUEUE_PORT, DEV_COUNT, 21, 3)\n REG32(RESPONSE_QUEUE_PORT, 0x10)\n+ FIELD(RESPONSE_QUEUE_PORT, DL, 0, 16)\n+ FIELD(RESPONSE_QUEUE_PORT, CCCT, 16, 8)\n+ FIELD(RESPONSE_QUEUE_PORT, TID, 24, 3)\n+ FIELD(RESPONSE_QUEUE_PORT, ERR_STATUS, 28, 4)\n REG32(RX_TX_DATA_PORT, 0x14)\n REG32(IBI_QUEUE_STATUS, 0x18)\n+ FIELD(IBI_QUEUE_STATUS, IBI_DATA_LEN, 0, 8)\n+ FIELD(IBI_QUEUE_STATUS, IBI_ID, 8, 8)\n+ FIELD(IBI_QUEUE_STATUS, LAST_STATUS, 24, 1)\n+ FIELD(IBI_QUEUE_STATUS, ERROR, 30, 1)\n+ FIELD(IBI_QUEUE_STATUS, IBI_STATUS, 31, 1)\n REG32(IBI_QUEUE_DATA, 0x18)\n REG32(QUEUE_THLD_CTRL, 0x1c)\n+ FIELD(QUEUE_THLD_CTRL, CMD_BUF_EMPTY_THLD, 0, 8);\n+ FIELD(QUEUE_THLD_CTRL, RESP_BUF_THLD, 8, 8);\n+ FIELD(QUEUE_THLD_CTRL, IBI_DATA_THLD, 16, 5);\n+ FIELD(QUEUE_THLD_CTRL, IBI_STATUS_THLD, 24, 8);\n REG32(DATA_BUFFER_THLD_CTRL, 0x20)\n+ FIELD(DATA_BUFFER_THLD_CTRL, TX_BUF_THLD, 0, 3)\n+ FIELD(DATA_BUFFER_THLD_CTRL, RX_BUF_THLD, 8, 3)\n+ FIELD(DATA_BUFFER_THLD_CTRL, TX_START_THLD, 16, 3)\n+ FIELD(DATA_BUFFER_THLD_CTRL, RX_START_THLD, 24, 3)\n REG32(IBI_QUEUE_CTRL, 0x24)\n+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_HOT_JOIN, 0, 1)\n+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_MASTER_REQ, 1, 1)\n+ FIELD(IBI_QUEUE_CTRL, NOTIFY_REJECTED_SLAVE_IRQ, 3, 1)\n REG32(IBI_MR_REQ_REJECT, 0x2c)\n REG32(IBI_SIR_REQ_REJECT, 0x30)\n REG32(RESET_CTRL, 0x34)\n+ FIELD(RESET_CTRL, CORE_RESET, 0, 1)\n+ FIELD(RESET_CTRL, CMD_QUEUE_RESET, 1, 1)\n+ FIELD(RESET_CTRL, RESP_QUEUE_RESET, 2, 1)\n+ FIELD(RESET_CTRL, TX_BUF_RESET, 3, 1)\n+ FIELD(RESET_CTRL, RX_BUF_RESET, 4, 1)\n+ FIELD(RESET_CTRL, IBI_QUEUE_RESET, 5, 1)\n REG32(SLV_EVENT_CTRL, 0x38)\n+ FIELD(SLV_EVENT_CTRL, SLV_INTERRUPT, 0, 1)\n+ FIELD(SLV_EVENT_CTRL, MASTER_INTERRUPT, 1, 1)\n+ FIELD(SLV_EVENT_CTRL, HOT_JOIN_INTERRUPT, 3, 1)\n+ FIELD(SLV_EVENT_CTRL, ACTIVITY_STATE, 4, 2)\n+ FIELD(SLV_EVENT_CTRL, MRL_UPDATED, 6, 1)\n+ FIELD(SLV_EVENT_CTRL, MWL_UPDATED, 7, 1)\n REG32(INTR_STATUS, 0x3c)\n+ FIELD(INTR_STATUS, TX_THLD, 0, 1)\n+ FIELD(INTR_STATUS, RX_THLD, 1, 1)\n+ FIELD(INTR_STATUS, IBI_THLD, 2, 1)\n+ FIELD(INTR_STATUS, CMD_QUEUE_RDY, 3, 1)\n+ FIELD(INTR_STATUS, RESP_RDY, 4, 1)\n+ FIELD(INTR_STATUS, TRANSFER_ABORT, 5, 1)\n+ FIELD(INTR_STATUS, CCC_UPDATED, 6, 1)\n+ FIELD(INTR_STATUS, DYN_ADDR_ASSGN, 8, 1)\n+ FIELD(INTR_STATUS, TRANSFER_ERR, 9, 1)\n+ FIELD(INTR_STATUS, DEFSLV, 10, 1)\n+ FIELD(INTR_STATUS, READ_REQ_RECV, 11, 1)\n+ FIELD(INTR_STATUS, IBI_UPDATED, 12, 1)\n+ FIELD(INTR_STATUS, BUSOWNER_UPDATED, 13, 1)\n REG32(INTR_STATUS_EN, 0x40)\n+ FIELD(INTR_STATUS_EN, TX_THLD, 0, 1)\n+ FIELD(INTR_STATUS_EN, RX_THLD, 1, 1)\n+ FIELD(INTR_STATUS_EN, IBI_THLD, 2, 1)\n+ FIELD(INTR_STATUS_EN, CMD_QUEUE_RDY, 3, 1)\n+ FIELD(INTR_STATUS_EN, RESP_RDY, 4, 1)\n+ FIELD(INTR_STATUS_EN, TRANSFER_ABORT, 5, 1)\n+ FIELD(INTR_STATUS_EN, CCC_UPDATED, 6, 1)\n+ FIELD(INTR_STATUS_EN, DYN_ADDR_ASSGN, 8, 1)\n+ FIELD(INTR_STATUS_EN, TRANSFER_ERR, 9, 1)\n+ FIELD(INTR_STATUS_EN, DEFSLV, 10, 1)\n+ FIELD(INTR_STATUS_EN, READ_REQ_RECV, 11, 1)\n+ FIELD(INTR_STATUS_EN, IBI_UPDATED, 12, 1)\n+ FIELD(INTR_STATUS_EN, BUSOWNER_UPDATED, 13, 1)\n REG32(INTR_SIGNAL_EN, 0x44)\n+ FIELD(INTR_SIGNAL_EN, TX_THLD, 0, 1)\n+ FIELD(INTR_SIGNAL_EN, RX_THLD, 1, 1)\n+ FIELD(INTR_SIGNAL_EN, IBI_THLD, 2, 1)\n+ FIELD(INTR_SIGNAL_EN, CMD_QUEUE_RDY, 3, 1)\n+ FIELD(INTR_SIGNAL_EN, RESP_RDY, 4, 1)\n+ FIELD(INTR_SIGNAL_EN, TRANSFER_ABORT, 5, 1)\n+ FIELD(INTR_SIGNAL_EN, CCC_UPDATED, 6, 1)\n+ FIELD(INTR_SIGNAL_EN, DYN_ADDR_ASSGN, 8, 1)\n+ FIELD(INTR_SIGNAL_EN, TRANSFER_ERR, 9, 1)\n+ FIELD(INTR_SIGNAL_EN, DEFSLV, 10, 1)\n+ FIELD(INTR_SIGNAL_EN, READ_REQ_RECV, 11, 1)\n+ FIELD(INTR_SIGNAL_EN, IBI_UPDATED, 12, 1)\n+ FIELD(INTR_SIGNAL_EN, BUSOWNER_UPDATED, 13, 1)\n REG32(INTR_FORCE, 0x48)\n+ FIELD(INTR_FORCE, TX_THLD, 0, 1)\n+ FIELD(INTR_FORCE, RX_THLD, 1, 1)\n+ FIELD(INTR_FORCE, IBI_THLD, 2, 1)\n+ FIELD(INTR_FORCE, CMD_QUEUE_RDY, 3, 1)\n+ FIELD(INTR_FORCE, RESP_RDY, 4, 1)\n+ FIELD(INTR_FORCE, TRANSFER_ABORT, 5, 1)\n+ FIELD(INTR_FORCE, CCC_UPDATED, 6, 1)\n+ FIELD(INTR_FORCE, DYN_ADDR_ASSGN, 8, 1)\n+ FIELD(INTR_FORCE, TRANSFER_ERR, 9, 1)\n+ FIELD(INTR_FORCE, DEFSLV, 10, 1)\n+ FIELD(INTR_FORCE, READ_REQ_RECV, 11, 1)\n+ FIELD(INTR_FORCE, IBI_UPDATED, 12, 1)\n+ FIELD(INTR_FORCE, BUSOWNER_UPDATED, 13, 1)\n REG32(QUEUE_STATUS_LEVEL, 0x4c)\n+ FIELD(QUEUE_STATUS_LEVEL, CMD_QUEUE_EMPTY_LOC, 0, 8)\n+ FIELD(QUEUE_STATUS_LEVEL, RESP_BUF_BLR, 8, 8)\n+ FIELD(QUEUE_STATUS_LEVEL, IBI_BUF_BLR, 16, 8)\n+ FIELD(QUEUE_STATUS_LEVEL, IBI_STATUS_CNT, 24, 5)\n REG32(DATA_BUFFER_STATUS_LEVEL, 0x50)\n+ FIELD(DATA_BUFFER_STATUS_LEVEL, TX_BUF_EMPTY_LOC, 0, 8)\n+ FIELD(DATA_BUFFER_STATUS_LEVEL, RX_BUF_BLR, 16, 8)\n REG32(PRESENT_STATE, 0x54)\n+ FIELD(PRESENT_STATE, SCL_LINE_SIGNAL_LEVEL, 0, 1)\n+ FIELD(PRESENT_STATE, SDA_LINE_SIGNAL_LEVEL, 1, 1)\n+ FIELD(PRESENT_STATE, CURRENT_MASTER, 2, 1)\n+ FIELD(PRESENT_STATE, CM_TFR_STATUS, 8, 6)\n+ FIELD(PRESENT_STATE, CM_TFR_ST_STATUS, 16, 6)\n+ FIELD(PRESENT_STATE, CMD_TID, 24, 4)\n REG32(CCC_DEVICE_STATUS, 0x58)\n+ FIELD(CCC_DEVICE_STATUS, PENDING_INTR, 0, 4)\n+ FIELD(CCC_DEVICE_STATUS, PROTOCOL_ERR, 5, 1)\n+ FIELD(CCC_DEVICE_STATUS, ACTIVITY_MODE, 6, 2)\n+ FIELD(CCC_DEVICE_STATUS, UNDER_ERR, 8, 1)\n+ FIELD(CCC_DEVICE_STATUS, SLV_BUSY, 9, 1)\n+ FIELD(CCC_DEVICE_STATUS, OVERFLOW_ERR, 10, 1)\n+ FIELD(CCC_DEVICE_STATUS, DATA_NOT_READY, 11, 1)\n+ FIELD(CCC_DEVICE_STATUS, BUFFER_NOT_AVAIL, 12, 1)\n REG32(DEVICE_ADDR_TABLE_POINTER, 0x5c)\n FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)\n FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR, 0, 16)\n REG32(DEV_CHAR_TABLE_POINTER, 0x60)\n+ FIELD(DEV_CHAR_TABLE_POINTER, P_DEV_CHAR_TABLE_START_ADDR, 0, 12)\n+ FIELD(DEV_CHAR_TABLE_POINTER, DEV_CHAR_TABLE_DEPTH, 12, 7)\n+ FIELD(DEV_CHAR_TABLE_POINTER, PRESENT_DEV_CHAR_TABLE_INDEX, 19, 3)\n REG32(VENDOR_SPECIFIC_REG_POINTER, 0x6c)\n+ FIELD(VENDOR_SPECIFIC_REG_POINTER, P_VENDOR_REG_START_ADDR, 0, 16)\n REG32(SLV_MIPI_PID_VALUE, 0x70)\n REG32(SLV_PID_VALUE, 0x74)\n+ FIELD(SLV_PID_VALUE, SLV_PID_DCR, 0, 12)\n+ FIELD(SLV_PID_VALUE, SLV_INST_ID, 12, 4)\n+ FIELD(SLV_PID_VALUE, SLV_PART_ID, 16, 16)\n REG32(SLV_CHAR_CTRL, 0x78)\n+ FIELD(SLV_CHAR_CTRL, BCR, 0, 8)\n+ FIELD(SLV_CHAR_CTRL, DCR, 8, 8)\n+ FIELD(SLV_CHAR_CTRL, HDR_CAP, 16, 8)\n REG32(SLV_MAX_LEN, 0x7c)\n+ FIELD(SLV_MAX_LEN, MWL, 0, 16)\n+ FIELD(SLV_MAX_LEN, MRL, 16, 16)\n REG32(MAX_READ_TURNAROUND, 0x80)\n REG32(MAX_DATA_SPEED, 0x84)\n REG32(SLV_DEBUG_STATUS, 0x88)\n REG32(SLV_INTR_REQ, 0x8c)\n+ FIELD(SLV_INTR_REQ, SIR, 0, 1)\n+ FIELD(SLV_INTR_REQ, SIR_CTRL, 1, 2)\n+ FIELD(SLV_INTR_REQ, MIR, 3, 1)\n+ FIELD(SLV_INTR_REQ, TS, 4, 1)\n+ FIELD(SLV_INTR_REQ, IBI_STS, 8, 2)\n+REG32(SLV_TSX_SYMBL_TIMING, 0x90)\n+ FIELD(SLV_TSX_SYMBL_TIMING, SLV_TSX_SYMBL_CNT, 0, 6)\n REG32(DEVICE_CTRL_EXTENDED, 0xb0)\n+ FIELD(DEVICE_CTRL_EXTENDED, MODE, 0, 2)\n+ FIELD(DEVICE_CTRL_EXTENDED, REQMST_ACK_CTRL, 3, 1)\n REG32(SCL_I3C_OD_TIMING, 0xb4)\n+ FIELD(SCL_I3C_OD_TIMING, I3C_OD_LCNT, 0, 8)\n+ FIELD(SCL_I3C_OD_TIMING, I3C_OD_HCNT, 16, 8)\n REG32(SCL_I3C_PP_TIMING, 0xb8)\n+ FIELD(SCL_I3C_PP_TIMING, I3C_PP_LCNT, 0, 8)\n+ FIELD(SCL_I3C_PP_TIMING, I3C_PP_HCNT, 16, 8)\n REG32(SCL_I2C_FM_TIMING, 0xbc)\n REG32(SCL_I2C_FMP_TIMING, 0xc0)\n+ FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_LCNT, 0, 16)\n+ FIELD(SCL_I2C_FMP_TIMING, I2C_FMP_HCNT, 16, 8)\n REG32(SCL_EXT_LCNT_TIMING, 0xc8)\n REG32(SCL_EXT_TERMN_LCNT_TIMING, 0xcc)\n REG32(BUS_FREE_TIMING, 0xd4)\n REG32(BUS_IDLE_TIMING, 0xd8)\n+ FIELD(BUS_IDLE_TIMING, BUS_IDLE_TIME, 0, 20)\n REG32(I3C_VER_ID, 0xe0)\n REG32(I3C_VER_TYPE, 0xe4)\n REG32(EXTENDED_CAPABILITY, 0xe8)\n REG32(SLAVE_CONFIG, 0xec)\n+/* Device characteristic table fields */\n+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC1, 0x200)\n+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, 0x200)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DYNAMIC_ADDR, 0, 8)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, DCR, 8, 8)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, BCR, 16, 8)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC_SECONDARY, STATIC_ADDR, 24, 8)\n+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC2, 0x204)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC2, MSB_PID, 0, 16)\n+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC3, 0x208)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, DCR, 0, 8)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC3, BCR, 8, 8)\n+REG32(DEVICE_CHARACTERISTIC_TABLE_LOC4, 0x20c)\n+ FIELD(DEVICE_CHARACTERISTIC_TABLE_LOC4, DEV_DYNAMIC_ADDR, 0, 8)\n+/* Dev addr table fields */\n+REG32(DEVICE_ADDR_TABLE_LOC1, 0x280)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_STATIC_ADDR, 0, 7)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_PEC_EN, 11, 1)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_WITH_DATA, 12, 1)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, SIR_REJECT, 13, 1)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, MR_REJECT, 14, 1)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_DYNAMIC_ADDR, 16, 8)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, IBI_ADDR_MASK, 24, 2)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, DEV_NACK_RETRY_CNT, 29, 2)\n+ FIELD(DEVICE_ADDR_TABLE_LOC1, LEGACY_I2C_DEVICE, 31, 1)\n \n static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = {\n [R_HW_CAPABILITY] = 0x000e00bf,\n", "prefixes": [ "v5", "05/21" ] }