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GET /api/patches/2194920/?format=api
{ "id": 2194920, "url": "http://patchwork.ozlabs.org/api/patches/2194920/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-19-jamin_lin@aspeedtech.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210091018.1553489-19-jamin_lin@aspeedtech.com>", "list_archive_url": null, "date": "2026-02-10T09:10:46", "name": "[v5,18/21] hw/i3c: Add Mock target", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5af5ca4f6553768ff100a9c2be4a2c5f66f519d7", "submitter": { "id": 81768, "url": "http://patchwork.ozlabs.org/api/people/81768/?format=api", "name": "Jamin Lin", "email": "jamin_lin@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210091018.1553489-19-jamin_lin@aspeedtech.com/mbox/", "series": [ { "id": 491625, "url": "http://patchwork.ozlabs.org/api/series/491625/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491625", "date": "2026-02-10T09:10:19", "name": "i3c: aspeed: Add I3C support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491625/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194920/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194920/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=Xx4Fvhs0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=GZjFS/hdvT8y2d1p3xi33JUio+UqLSU4JtKs354VCAg=;\n b=zHfDgRVpBXBcloIU5LEOzL0VsALbMbkuPLgXESYbqSqbXa2i5i35OEk0qJv/oJWiQtcMwHyEUM49yUlsCQrBGm53i1kV8uuXAmNuXgXXdA4X8qxezR+TM67YcV6+MqjMvcyyIqUlVKtLq4MJhoZR+pzvMlIz1bNy1JcT5LVXYAWtmM8xG2P0GpmQOL0M3z2PKd9WWDQsuRNxpj8P0h3mtZsHqpmRyaMSfH92BWSvtV4TYSCeBXcFnFPJCo2FzjR4RO3c3DCWsaIZQnuGYBZN3o9VKaGlUAuPH8y4umCNZLKTJw1uR+Nftd26OgK53oBiwpQSj4YcyGzjDKjEfxmWDA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=aspeedtech.com; dmarc=pass action=none\n header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=GZjFS/hdvT8y2d1p3xi33JUio+UqLSU4JtKs354VCAg=;\n b=Xx4Fvhs0zAzpQwpX8v0dl97+IzJVCq855/jF1fg9IJc9/UFljM7ht1s3ZQyM8trHzcNL+qVULdm+wEIrjZrSwS9H1s0t8gN/OANHotzhUkvX3eLcFUDSXf/PgKAxfNTqT0r2KRidTZk9VAoENFUOInEab796v58vqcGlV8NF/zjwuTuHb6g6axqWEN1oJwTbesa9CLDmAoYTx/YfcChHj//uuHaiZ+0HRpg2qyJ2mJOX2FCOVatK18TkSJA3YWOne5QUwO/ikRZzWsLHVW33q1RO9Jt5m1IPvpOH4I9EI/yn4WiC2mxv56qfZEUgg2ypiC/qBs2dBnef+9wp0Xz2dQ==", "From": "Jamin Lin <jamin_lin@aspeedtech.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n =?iso-8859-1?q?C=E9dric_Le_Goater?= <clg@kaod.org>,\n Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>,\n Andrew Jeffery <andrew@codeconstruct.com.au>, Joel Stanley <joel@jms.id.au>,\n\t=?iso-8859-1?q?Marc-Andr=E9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?iso-8859-1?q?Daniel_P=2E_Berrang=E9?= <berrange@redhat.com>,\n\t=?iso-8859-1?q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,\n \"open list:All patches CC here\" <qemu-devel@nongnu.org>,\n \"open list:ARM TCG CPUs\" <qemu-arm@nongnu.org>", "CC": "Jamin Lin <jamin_lin@aspeedtech.com>, Troy Lee <troy_lee@aspeedtech.com>,\n Kane Chen <kane_chen@aspeedtech.com>, \"nabihestefan@google.com\"\n <nabihestefan@google.com>, Joe Komlodi <komlodi@google.com>, Titus Rwantare\n <titusr@google.com>, Patrick Venture <venture@google.com>", "Subject": "[PATCH v5 18/21] hw/i3c: Add Mock target", "Thread-Topic": "[PATCH v5 18/21] hw/i3c: Add Mock target", "Thread-Index": "AQHcmm0kEufGdnpVB0yRA+lK+teccg==", "Date": "Tue, 10 Feb 2026 09:10:46 +0000", "Message-ID": "<20260210091018.1553489-19-jamin_lin@aspeedtech.com>", "References": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "In-Reply-To": "<20260210091018.1553489-1-jamin_lin@aspeedtech.com>", "Accept-Language": "zh-TW, en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=Xx4Fvhs0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "aspeedtech.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "TYPPR06MB8206.apcprd06.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 56b3074b-9bf8-433d-b191-08de688446a6", "X-MS-Exchange-CrossTenant-originalarrivaltime": "10 Feb 2026 09:10:46.2976 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "43d4aa98-e35b-4575-8939-080e90d5a249", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n i+nfbjOfc87Ir0Jbziha/m6kkRhPBVbwEo/nT2qRZd7L7maSmCsbXIs5MyMbNfEb65zfarJFjGTaumO6o2IED4RnyL/yF1LcvQ2ZW+A2BDk=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "KUZPR06MB8268", "Received-SPF": "pass client-ip=2a01:111:f403:c40f::6;\n envelope-from=jamin_lin@aspeedtech.com;\n helo=SEYPR02CU001.outbound.protection.outlook.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Adds a simple i3c device to be used for testing in lieu of a real\ndevice.\n\nThe mock target supports the following features:\n- A buffer that users can read and write to.\n- CCC support for commonly used CCCs when probing devices on an I3C bus.\n- IBI sending upon receiving a user-defined byte.\n\nSigned-off-by: Joe Komlodi <komlodi@google.com>\nReviewed-by: Titus Rwantare <titusr@google.com>\nReviewed-by: Patrick Venture <venture@google.com>\nReviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>\nSigned-off-by: Jamin Lin <jamin_lin@aspeedtech.com>\n---\n include/hw/i3c/mock-i3c-target.h | 52 ++++++\n hw/i3c/mock-i3c-target.c | 298 +++++++++++++++++++++++++++++++\n hw/i3c/Kconfig | 10 ++\n hw/i3c/meson.build | 1 +\n hw/i3c/trace-events | 10 ++\n 5 files changed, 371 insertions(+)\n create mode 100644 include/hw/i3c/mock-i3c-target.h\n create mode 100644 hw/i3c/mock-i3c-target.c", "diff": "diff --git a/include/hw/i3c/mock-i3c-target.h b/include/hw/i3c/mock-i3c-target.h\nnew file mode 100644\nindex 0000000000..8c6003ae8b\n--- /dev/null\n+++ b/include/hw/i3c/mock-i3c-target.h\n@@ -0,0 +1,52 @@\n+#ifndef MOCK_I3C_TARGET_H_\n+#define MOCK_I3C_TARGET_H_\n+\n+/*\n+ * Mock I3C Device\n+ *\n+ * Copyright (c) 2025 Google LLC\n+ *\n+ * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,\n+ * and the pointer in the buffer is reset to 0 on an I3C STOP.\n+ * To write to the buffer, issue a private write and send data.\n+ * To read from the buffer, issue a private read.\n+ *\n+ * The mock target also supports sending target interrupt IBIs.\n+ * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and\n+ * send that number in a private transaction. The mock target will issue an IBI\n+ * after 1 second.\n+ *\n+ * It also supports a handful of CCCs that are typically used when probing I3C\n+ * devices.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/timer.h\"\n+#include \"hw/i3c/i3c.h\"\n+\n+#define TYPE_MOCK_I3C_TARGET \"mock-i3c-target\"\n+OBJECT_DECLARE_SIMPLE_TYPE(MockI3cTargetState, MOCK_I3C_TARGET)\n+\n+struct MockI3cTargetState {\n+ I3CTarget parent_obj;\n+\n+ /* General device state */\n+ bool can_ibi;\n+ QEMUTimer qtimer;\n+ size_t p_buf;\n+ uint8_t *buf;\n+\n+ /* For Handing CCCs. */\n+ bool in_ccc;\n+ I3CCCC curr_ccc;\n+ uint8_t ccc_byte_offset;\n+\n+ struct {\n+ uint32_t buf_size;\n+ uint8_t ibi_magic;\n+ } cfg;\n+};\n+\n+#endif\ndiff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c\nnew file mode 100644\nindex 0000000000..875cd7c7d0\n--- /dev/null\n+++ b/hw/i3c/mock-i3c-target.c\n@@ -0,0 +1,298 @@\n+/*\n+ * Mock I3C Device\n+ *\n+ * Copyright (c) 2025 Google LLC\n+ *\n+ * The mock I3C device can be thought of as a simple EEPROM. It has a buffer,\n+ * and the pointer in the buffer is reset to 0 on an I3C STOP.\n+ * To write to the buffer, issue a private write and send data.\n+ * To read from the buffer, issue a private read.\n+ *\n+ * The mock target also supports sending target interrupt IBIs.\n+ * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number, and\n+ * send that number in a private transaction. The mock target will issue an IBI\n+ * after 1 second.\n+ *\n+ * It also supports a handful of CCCs that are typically used when probing I3C\n+ * devices.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"trace.h\"\n+#include \"hw/i3c/i3c.h\"\n+#include \"hw/i3c/mock-i3c-target.h\"\n+#include \"hw/core/irq.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu/module.h\"\n+\n+#define IBI_DELAY_NS (1 * 1000 * 1000)\n+\n+static uint32_t mock_i3c_target_rx(I3CTarget *i3c, uint8_t *data,\n+ uint32_t num_to_read)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+ uint32_t i;\n+\n+ /* Bounds check. */\n+ if (s->p_buf == s->cfg.buf_size) {\n+ return 0;\n+ }\n+\n+ for (i = 0; i < num_to_read; i++) {\n+ data[i] = s->buf[s->p_buf];\n+ trace_mock_i3c_target_rx(data[i]);\n+ s->p_buf++;\n+ if (s->p_buf == s->cfg.buf_size) {\n+ break;\n+ }\n+ }\n+\n+ /* Return the number of bytes we're sending to the controller. */\n+ return i;\n+}\n+\n+static void mock_i3c_target_ibi_timer_start(MockI3cTargetState *s)\n+{\n+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);\n+ timer_mod(&s->qtimer, now + IBI_DELAY_NS);\n+}\n+\n+static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data,\n+ uint32_t num_to_send, uint32_t *num_sent)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+ int ret;\n+ uint32_t to_write;\n+\n+ if (s->cfg.ibi_magic && num_to_send == 1 && s->cfg.ibi_magic == *data) {\n+ mock_i3c_target_ibi_timer_start(s);\n+ return 0;\n+ }\n+\n+ /* Bounds check. */\n+ if (num_to_send + s->p_buf > s->cfg.buf_size) {\n+ to_write = s->cfg.buf_size - s->p_buf;\n+ ret = -1;\n+ } else {\n+ to_write = num_to_send;\n+ ret = 0;\n+ }\n+ for (uint32_t i = 0; i < to_write; i++) {\n+ trace_mock_i3c_target_tx(data[i]);\n+ s->buf[s->p_buf] = data[i];\n+ s->p_buf++;\n+ }\n+ return ret;\n+}\n+\n+static int mock_i3c_target_event(I3CTarget *i3c, enum I3CEvent event)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+\n+ trace_mock_i3c_target_event(event);\n+ if (event == I3C_STOP) {\n+ s->in_ccc = false;\n+ s->curr_ccc = 0;\n+ s->ccc_byte_offset = 0;\n+ s->p_buf = 0;\n+ }\n+\n+ return 0;\n+}\n+\n+static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data,\n+ uint32_t num_to_read,\n+ uint32_t *num_read)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+\n+ switch (s->curr_ccc) {\n+ case I3C_CCCD_GETMXDS:\n+ /* Default data rate for I3C. */\n+ while (s->ccc_byte_offset < num_to_read) {\n+ if (s->ccc_byte_offset >= 2) {\n+ break;\n+ }\n+ data[s->ccc_byte_offset] = 0;\n+ *num_read = s->ccc_byte_offset;\n+ s->ccc_byte_offset++;\n+ }\n+ break;\n+ case I3C_CCCD_GETCAPS:\n+ /* Support I3C version 1.1.x, no other features. */\n+ while (s->ccc_byte_offset < num_to_read) {\n+ if (s->ccc_byte_offset >= 2) {\n+ break;\n+ }\n+ if (s->ccc_byte_offset == 0) {\n+ data[s->ccc_byte_offset] = 0;\n+ } else {\n+ data[s->ccc_byte_offset] = 0x01;\n+ }\n+ *num_read = s->ccc_byte_offset;\n+ s->ccc_byte_offset++;\n+ }\n+ break;\n+ case I3C_CCCD_GETMWL:\n+ case I3C_CCCD_GETMRL:\n+ /* MWL/MRL is MSB first. */\n+ while (s->ccc_byte_offset < num_to_read) {\n+ if (s->ccc_byte_offset >= 2) {\n+ break;\n+ }\n+ data[s->ccc_byte_offset] = (s->cfg.buf_size &\n+ (0xff00 >> (s->ccc_byte_offset * 8))) >>\n+ (8 - (s->ccc_byte_offset * 8));\n+ s->ccc_byte_offset++;\n+ *num_read = num_to_read;\n+ }\n+ break;\n+ case I3C_CCC_ENTDAA:\n+ case I3C_CCCD_GETPID:\n+ case I3C_CCCD_GETBCR:\n+ case I3C_CCCD_GETDCR:\n+ /* Nothing to do. */\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"Unhandled CCC 0x%.2x\\n\", s->curr_ccc);\n+ return -1;\n+ }\n+\n+ trace_mock_i3c_target_handle_ccc_read(*num_read, num_to_read);\n+ return 0;\n+}\n+\n+static int mock_i3c_target_handle_ccc_write(I3CTarget *i3c, const uint8_t *data,\n+ uint32_t num_to_send,\n+ uint32_t *num_sent)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+\n+ if (!s->curr_ccc) {\n+ s->in_ccc = true;\n+ s->curr_ccc = *data;\n+ trace_mock_i3c_target_new_ccc(s->curr_ccc);\n+ }\n+\n+ *num_sent = 1;\n+ switch (s->curr_ccc) {\n+ case I3C_CCC_ENEC:\n+ case I3C_CCCD_ENEC:\n+ s->can_ibi = true;\n+ break;\n+ case I3C_CCC_DISEC:\n+ case I3C_CCCD_DISEC:\n+ s->can_ibi = false;\n+ break;\n+ case I3C_CCC_ENTDAA:\n+ case I3C_CCC_SETAASA:\n+ case I3C_CCC_RSTDAA:\n+ case I3C_CCCD_SETDASA:\n+ case I3C_CCCD_GETPID:\n+ case I3C_CCCD_GETBCR:\n+ case I3C_CCCD_GETDCR:\n+ case I3C_CCCD_GETMWL:\n+ case I3C_CCCD_GETMRL:\n+ case I3C_CCCD_GETMXDS:\n+ case I3C_CCCD_GETCAPS:\n+ /* Nothing to do. */\n+ break;\n+ default:\n+ qemu_log_mask(LOG_GUEST_ERROR, \"Unhandled CCC 0x%.2x\\n\", s->curr_ccc);\n+ return -1;\n+ }\n+\n+ trace_mock_i3c_target_handle_ccc_write(*num_sent, num_to_send);\n+ return 0;\n+}\n+\n+static void mock_i3c_target_do_ibi(MockI3cTargetState *s)\n+{\n+ if (!s->can_ibi) {\n+ return;\n+ }\n+\n+ trace_mock_i3c_target_do_ibi(s->parent_obj.address, true);\n+ int nack = i3c_target_send_ibi(&s->parent_obj, s->parent_obj.address,\n+ /*is_recv=*/true);\n+ /* Getting NACKed isn't necessarily an error, just print it out. */\n+ if (nack) {\n+ trace_mock_i3c_target_do_ibi_nack(\"sending\");\n+ }\n+ nack = i3c_target_ibi_finish(&s->parent_obj, 0x00);\n+ if (nack) {\n+ trace_mock_i3c_target_do_ibi_nack(\"finishing\");\n+ }\n+}\n+\n+static void mock_i3c_target_timer_elapsed(void *opaque)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(opaque);\n+ timer_del(&s->qtimer);\n+ mock_i3c_target_do_ibi(s);\n+}\n+\n+static void mock_i3c_target_reset(I3CTarget *i3c)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(i3c);\n+ s->can_ibi = false;\n+}\n+\n+static void mock_i3c_target_realize(DeviceState *dev, Error **errp)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(dev);\n+ s->buf = g_new0(uint8_t, s->cfg.buf_size);\n+ mock_i3c_target_reset(&s->parent_obj);\n+}\n+\n+static void mock_i3c_target_init(Object *obj)\n+{\n+ MockI3cTargetState *s = MOCK_I3C_TARGET(obj);\n+ s->can_ibi = false;\n+\n+ /* For IBIs. */\n+ timer_init_ns(&s->qtimer, QEMU_CLOCK_VIRTUAL, mock_i3c_target_timer_elapsed,\n+ s);\n+}\n+\n+static const Property remote_i3c_props[] = {\n+ /* The size of the internal buffer. */\n+ DEFINE_PROP_UINT32(\"buf-size\", MockI3cTargetState, cfg.buf_size, 0x100),\n+ /*\n+ * If the mock target receives this number, it will issue an IBI after\n+ * 1 second. Disabled if the IBI magic number is 0.\n+ */\n+ DEFINE_PROP_UINT8(\"ibi-magic-num\", MockI3cTargetState, cfg.ibi_magic, 0x00),\n+};\n+\n+static void mock_i3c_target_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ I3CTargetClass *k = I3C_TARGET_CLASS(klass);\n+\n+ dc->realize = mock_i3c_target_realize;\n+ k->event = mock_i3c_target_event;\n+ k->recv = mock_i3c_target_rx;\n+ k->send = mock_i3c_target_tx;\n+ k->handle_ccc_read = mock_i3c_target_handle_ccc_read;\n+ k->handle_ccc_write = mock_i3c_target_handle_ccc_write;\n+\n+ device_class_set_props(dc, remote_i3c_props);\n+}\n+\n+static const TypeInfo mock_i3c_target_types[] = {\n+ {\n+ .name = TYPE_MOCK_I3C_TARGET,\n+ .parent = TYPE_I3C_TARGET,\n+ .instance_size = sizeof(MockI3cTargetState),\n+ .instance_init = mock_i3c_target_init,\n+ .class_init = mock_i3c_target_class_init,\n+ },\n+};\n+\n+DEFINE_TYPES(mock_i3c_target_types)\n+\ndiff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig\nindex ecec77d6fc..d5c6d4049b 100644\n--- a/hw/i3c/Kconfig\n+++ b/hw/i3c/Kconfig\n@@ -3,3 +3,13 @@ config I3C\n \n config DW_I3C\n bool\n+\n+config I3C_DEVICES\n+ # Device group for i3c devices which can reasonably be user-plugged to any\n+ # board's i3c bus.\n+ bool\n+\n+config MOCK_I3C_TARGET\n+ bool\n+ select I3C\n+ default y if I3C_DEVICES\ndiff --git a/hw/i3c/meson.build b/hw/i3c/meson.build\nindex 83d75e7d5c..e614b18712 100644\n--- a/hw/i3c/meson.build\n+++ b/hw/i3c/meson.build\n@@ -2,4 +2,5 @@ i3c_ss = ss.source_set()\n i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c'))\n i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c'))\n i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c'))\n+i3c_ss.add(when: 'CONFIG_MOCK_I3C_TARGET', if_true: files('mock-i3c-target.c'))\n system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss)\ndiff --git a/hw/i3c/trace-events b/hw/i3c/trace-events\nindex 39f33d9a50..9e58edec99 100644\n--- a/hw/i3c/trace-events\n+++ b/hw/i3c/trace-events\n@@ -36,3 +36,13 @@ legacy_i2c_recv(uint8_t byte) \"Legacy I2C recv 0x%\" PRIx8\n legacy_i2c_send(uint8_t byte) \"Legacy I2C send 0x%\" PRIx8\n legacy_i2c_start_transfer(uint8_t address, bool is_recv) \"Legacy I2C START with address 0x%\" PRIx8 \" is_recv=%d\"\n legacy_i2c_end_transfer(void) \"Legacy I2C STOP\"\n+\n+# mock-target.c\n+mock_i3c_target_rx(uint8_t byte) \"I3C mock target read 0x%\" PRIx8\n+mock_i3c_target_tx(uint8_t byte) \"I3C mock target write 0x%\" PRIx8\n+mock_i3c_target_event(uint8_t event) \"I3C mock target event 0x%\" PRIx8\n+mock_i3c_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) \"I3C mock target read %\" PRId32 \"/%\" PRId32 \" bytes\"\n+mock_i3c_target_new_ccc(uint8_t ccc) \"I3C mock target handle CCC 0x%\" PRIx8\n+mock_i3c_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) \"I3C mock target send %\" PRId32 \"/%\" PRId32 \" bytes\"\n+mock_i3c_target_do_ibi(uint8_t address, bool is_recv) \"I3C mock target IBI with address 0x%\" PRIx8 \" RnW=%d\"\n+mock_i3c_target_do_ibi_nack(const char *reason) \"NACKed from controller when %s target interrupt\"\n", "prefixes": [ "v5", "18/21" ] }