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GET /api/patches/2194849/?format=api
{ "id": 2194849, "url": "http://patchwork.ozlabs.org/api/patches/2194849/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210032348.987549-22-zhao1.liu@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210032348.987549-22-zhao1.liu@intel.com>", "list_archive_url": null, "date": "2026-02-10T03:23:48", "name": "[v2,21/21] hw/core/qdev-properties: support valid default value for DEFINE_PROP_UINT64_CHECKMASK", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1f17e01d7234030245628490b1964025496d8f5b", "submitter": { "id": 86545, "url": "http://patchwork.ozlabs.org/api/people/86545/?format=api", "name": "Zhao Liu", "email": "zhao1.liu@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210032348.987549-22-zhao1.liu@intel.com/mbox/", "series": [ { "id": 491594, "url": "http://patchwork.ozlabs.org/api/series/491594/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491594", "date": "2026-02-10T03:23:28", "name": "qom: introduce property flags to track external user input", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491594/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194849/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194849/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=FTCQRrhl;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95sV2dcGz1xwH\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 14:00:30 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpdz8-0001m9-FZ; Mon, 09 Feb 2026 22:00:18 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhao1.liu@intel.com>)\n id 1vpdyp-0001FT-2m\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 22:00:04 -0500", "from mgamail.intel.com ([198.175.65.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhao1.liu@intel.com>)\n id 1vpdyj-0004En-8w\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:59:56 -0500", "from orviesa008.jf.intel.com ([10.64.159.148])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Feb 2026 18:59:52 -0800", "from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39])\n by orviesa008.jf.intel.com with ESMTP; 09 Feb 2026 18:59:48 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1770692393; x=1802228393;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=k4278D/unK5bwhnrNdxt3ByvRIvl2uTcZ+7sAYt5EQ8=;\n b=FTCQRrhlGPaeb6EDicFIoNZ8bnxUx1Hzm6NT1O5Vzf9+lLZ37evmDVss\n E0N3htA0YzNNNCiHcCtCaaZSi2NeVaje96Xmutp7/YD67AO3B0ejICUUA\n XhMF3YjfQHdiS+ffqG5EM1Zp9poS5+kaKJGGVdeM3fQS9je8GYzvQR+7o\n fW+gt8XnZWnPgmFMdjKG1bxeAWRC5m143VD7FpfvV61fMGGfMz3R3ezEf\n VtPAhmajQrYmLUXoPhXmAx2rhOy4JQJT0j2Gm0jP2oVJZCTzNbBnfECGN\n jCKGk8evC1UdgXutgYTu4gkWr8xasd7A+hhmdQ7X1JFmid4E07PjQWGX2 Q==;", "X-CSE-ConnectionGUID": [ "LhZvm5wETU6soCoDWHn4aQ==", "R1aMdRTGRnSweM0ElxSd+Q==" ], "X-CSE-MsgGUID": [ "YuQwNruzQ2C4TA/xXjl/IA==", "rOuhMUKASpSp2/7FEzorpg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11696\"; a=\"75660026\"", "E=Sophos;i=\"6.21,283,1763452800\"; d=\"scan'208\";a=\"75660026\"", "E=Sophos;i=\"6.21,283,1763452800\"; d=\"scan'208\";a=\"211800818\"" ], "X-ExtLoop1": "1", "From": "Zhao Liu <zhao1.liu@intel.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>, =?utf-8?q?Daniel_P_=2E_Berrang?=\n\t=?utf-8?q?=C3=A9?= <berrange@redhat.com>,\n Eduardo Habkost <eduardo@habkost.net>, Markus Armbruster <armbru@redhat.com>,\n Thomas Huth <thuth@redhat.com>, Igor Mammedov <imammedo@redhat.com>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Cc": "Richard Henderson <richard.henderson@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n \"Michael S . Tsirkin\" <mst@redhat.com>,\n BALATON Zoltan <balaton@eik.bme.hu>,\n Mark Cave-Ayland <mark.caveayland@nutanix.com>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Zide Chen <zide.chen@intel.com>, Dapeng Mi <dapeng1.mi@linux.intel.com>,\n Zhao Liu <zhao1.liu@intel.com>, qemu-devel@nongnu.org,\n devel@lists.libvirt.org", "Subject": "[PATCH v2 21/21] hw/core/qdev-properties: support valid default value\n for DEFINE_PROP_UINT64_CHECKMASK", "Date": "Tue, 10 Feb 2026 11:23:48 +0800", "Message-Id": "<20260210032348.987549-22-zhao1.liu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260210032348.987549-1-zhao1.liu@intel.com>", "References": "<20260210032348.987549-1-zhao1.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com;\n helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "DEFINE_PROP_UINT64_CHECKMASK is designed to detect and check user's\nproperty setting:\n * checking: check property value against a bitmask.\n * detection: ask caller to provide an invalid value as the initial\n \"sentinel\" value, which is impossible to be set by users. However,\n this detection is not strict, since the property could be also\n set internally.\n\nThe entire mechanism is not easy to use.\n\nNow there's USER_SET flag in place (and the current unique use case\n\"lbr-fmt\" has been converted to checking USER_SET way), manual setting\nof invalid initial values is no longer required.\n\nThus, extend DEFINE_PROP_UINT64_CHECKMASK to support *valid* default\nvalue, and for \"lbr-fmt\" case, replace the invalid initialization value\n`~PERF_CAP_LBR_FMT` with a valid value `0`.\n\nIn addition, considering DEFINE_PROP_UINT64_CHECKMASK itself actually\ndoesn't identify whether the property is set by the user or not, remove\n\"user-supplied\" related description in its document.\n\nSigned-off-by: Zhao Liu <zhao1.liu@intel.com>\n---\n hw/core/qdev-properties.c | 1 +\n include/hw/core/qdev-properties.h | 14 +++++++-------\n target/i386/cpu.c | 4 +---\n 3 files changed, 9 insertions(+), 10 deletions(-)", "diff": "diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c\nindex 91c4010e7dc9..b84214e60f19 100644\n--- a/hw/core/qdev-properties.c\n+++ b/hw/core/qdev-properties.c\n@@ -507,6 +507,7 @@ const PropertyInfo qdev_prop_uint64_checkmask = {\n .type = \"uint64\",\n .get = get_uint64,\n .set = set_uint64_checkmask,\n+ .set_default_value = qdev_propinfo_set_default_value_uint,\n };\n \n /* --- pointer-size integer --- */\ndiff --git a/include/hw/core/qdev-properties.h b/include/hw/core/qdev-properties.h\nindex c06de37b1e9d..2ac784bb5e9c 100644\n--- a/include/hw/core/qdev-properties.h\n+++ b/include/hw/core/qdev-properties.h\n@@ -128,14 +128,14 @@ extern const PropertyInfo qdev_prop_link;\n ##__VA_ARGS__)\n \n /**\n- * The DEFINE_PROP_UINT64_CHECKMASK macro checks a user-supplied value\n- * against corresponding bitmask, rejects the value if it violates.\n- * The default value is set in instance_init().\n+ * The DEFINE_PROP_UINT64_CHECKMASK macro checks a value against corresponding\n+ * bitmask, rejects the value if it violates.\n */\n-#define DEFINE_PROP_UINT64_CHECKMASK(_name, _state, _field, _bitmask) \\\n- DEFINE_PROP(_name, _state, _field, qdev_prop_uint64_checkmask, uint64_t, \\\n- .bitmask = (_bitmask), \\\n- .set_default = false)\n+#define DEFINE_PROP_UINT64_CHECKMASK(_name, _state, _field, _bitmask, _defval) \\\n+ DEFINE_PROP(_name, _state, _field, qdev_prop_uint64_checkmask, uint64_t, \\\n+ .bitmask = (_bitmask), \\\n+ .set_default = true, \\\n+ .defval.u = (_defval))\n \n /**\n * DEFINE_PROP_ARRAY:\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex a6d943c53a3f..56735570d66c 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -10265,9 +10265,7 @@ static void x86_cpu_initfn(Object *obj)\n object_property_add_alias(obj, \"pause_filter\", obj, \"pause-filter\");\n object_property_add_alias(obj, \"sse4_1\", obj, \"sse4.1\");\n object_property_add_alias(obj, \"sse4_2\", obj, \"sse4.2\");\n-\n object_property_add_alias(obj, \"hv-apicv\", obj, \"hv-avic\");\n- cpu->lbr_fmt = ~PERF_CAP_LBR_FMT;\n object_property_add_alias(obj, \"lbr_fmt\", obj, \"lbr-fmt\");\n \n if (xcc->model) {\n@@ -10439,7 +10437,7 @@ static const Property x86_cpu_properties[] = {\n #endif\n DEFINE_PROP_INT32(\"node-id\", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),\n DEFINE_PROP_BOOL(\"pmu\", X86CPU, enable_pmu, false),\n- DEFINE_PROP_UINT64_CHECKMASK(\"lbr-fmt\", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT),\n+ DEFINE_PROP_UINT64_CHECKMASK(\"lbr-fmt\", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT, 0),\n \n DEFINE_PROP_UINT32(\"hv-spinlocks\", X86CPU, hyperv_spinlock_attempts,\n HYPERV_SPINLOCK_NEVER_NOTIFY),\n", "prefixes": [ "v2", "21/21" ] }