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GET /api/patches/2194847/?format=api
{ "id": 2194847, "url": "http://patchwork.ozlabs.org/api/patches/2194847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210032348.987549-16-zhao1.liu@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210032348.987549-16-zhao1.liu@intel.com>", "list_archive_url": null, "date": "2026-02-10T03:23:42", "name": "[v2,15/21] target/i386: deprecate fill-mtrr-mask property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bb28a6a6d66e9c986b3c5f2d76fef71485f60431", "submitter": { "id": 86545, "url": "http://patchwork.ozlabs.org/api/people/86545/?format=api", "name": "Zhao Liu", "email": "zhao1.liu@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210032348.987549-16-zhao1.liu@intel.com/mbox/", "series": [ { "id": 491594, "url": "http://patchwork.ozlabs.org/api/series/491594/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491594", "date": "2026-02-10T03:23:28", "name": "qom: introduce property flags to track external user input", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491594/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194847/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194847/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=O2C/5h6L;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95sS3Tv7z1xvb\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 14:00:28 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpdyX-0008Vl-4y; Mon, 09 Feb 2026 21:59:41 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhao1.liu@intel.com>)\n id 1vpdyK-00086v-Rs\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:59:31 -0500", "from mgamail.intel.com ([198.175.65.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhao1.liu@intel.com>)\n id 1vpdyJ-0004En-25\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:59:28 -0500", "from orviesa008.jf.intel.com ([10.64.159.148])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Feb 2026 18:59:24 -0800", "from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39])\n by orviesa008.jf.intel.com with ESMTP; 09 Feb 2026 18:59:21 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1770692367; x=1802228367;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=FzssT/Ir75O6xe5arR/QxgvvLYXw6aFHUgJgDoyi+Mw=;\n b=O2C/5h6L+J/xCyZbIKXZ7ScV78DmXuEBqnUullBNb8JiyJLS28G1geeN\n C0y3nwtsbrsrn/SCa1W7j3q7kfUNuznwA4lg5GkNajAWYkaNfhgT5mcF4\n IsAQFAlPXtkz8xcHT3LjsHJVqs25wxgt9rUU9hfsxSD/pvz/iQdznYJd6\n 5WVlj+nVgAiXid/lvMmzAPj+UgItuyPNLJW+zRAzeTyjocgcQ/W06XfGQ\n 3x7FXU/qD0rXts8CXoXOEdI9I9fPP0akGqg4s2KX9hIzSc0WnqV27ZGWz\n h++B0xiNnqTCfsbPuQ6J5XdJlJKuO7Gzxz0xsOy8D/878VkRopj2nv13k w==;", "X-CSE-ConnectionGUID": [ "WShSdb0fRPO/GcVe2YxasA==", "s6QsOcZURWusmf9pAMQlXA==" ], "X-CSE-MsgGUID": [ "S8tzyPE+SDKdCRQl3iFlFQ==", "mYGrl1f/SqmV4GCjCAv9nQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11696\"; a=\"75659961\"", "E=Sophos;i=\"6.21,283,1763452800\"; d=\"scan'208\";a=\"75659961\"", "E=Sophos;i=\"6.21,283,1763452800\"; d=\"scan'208\";a=\"211800711\"" ], "X-ExtLoop1": "1", "From": "Zhao Liu <zhao1.liu@intel.com>", "To": "Paolo Bonzini <pbonzini@redhat.com>, =?utf-8?q?Daniel_P_=2E_Berrang?=\n\t=?utf-8?q?=C3=A9?= <berrange@redhat.com>,\n Eduardo Habkost <eduardo@habkost.net>, Markus Armbruster <armbru@redhat.com>,\n Thomas Huth <thuth@redhat.com>, Igor Mammedov <imammedo@redhat.com>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Cc": "Richard Henderson <richard.henderson@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n \"Michael S . Tsirkin\" <mst@redhat.com>,\n BALATON Zoltan <balaton@eik.bme.hu>,\n Mark Cave-Ayland <mark.caveayland@nutanix.com>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Zide Chen <zide.chen@intel.com>, Dapeng Mi <dapeng1.mi@linux.intel.com>,\n Zhao Liu <zhao1.liu@intel.com>, qemu-devel@nongnu.org,\n devel@lists.libvirt.org", "Subject": "[PATCH v2 15/21] target/i386: deprecate fill-mtrr-mask property", "Date": "Tue, 10 Feb 2026 11:23:42 +0800", "Message-Id": "<20260210032348.987549-16-zhao1.liu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260210032348.987549-1-zhao1.liu@intel.com>", "References": "<20260210032348.987549-1-zhao1.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com;\n helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "\"fill-mtee-mask\" was previously disabled only on PC-Q35-2.6 and\nPC-I440FX-2.6 machines, but PC v2.6 machines have been deprecated and\nwill be removed.\n\nConsiderring it may have external use, so deprecate it before removal.\n\nSigned-off-by: Zhao Liu <zhao1.liu@intel.com>\n---\n docs/about/deprecated.rst | 8 ++++++++\n target/i386/cpu.c | 3 ++-\n 2 files changed, 10 insertions(+), 1 deletion(-)", "diff": "diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst\nindex 1d5c4f3707cb..0e8a25e37414 100644\n--- a/docs/about/deprecated.rst\n+++ b/docs/about/deprecated.rst\n@@ -448,6 +448,14 @@ Backend ``memory`` (since 9.0)\n CPU device properties\n '''''''''''''''''''''\n \n+``fill-mtrr-mask`` on x86 (since 11.0)\n+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n+\n+The ``fill-mtrr-mask=true`` fill the bits between 51..number-of-physical-address\n+-bits in the MTRR_PHYSMASKn variable range mtrr masks. It was previously set to\n+false only on PC-Q35-2.6 and PC-I440FX-2.6 machines, but PC v2.6 machines have\n+been removed. Deprecate this property to stop external use.\n+\n ``pmu-num=n`` on RISC-V CPUs (since 8.2)\n ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n \ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex 94a9dcde1eb1..13ccb1702d32 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -10510,7 +10510,8 @@ static const Property x86_cpu_properties[] = {\n DEFINE_PROP_UINT32(\"guest-phys-bits\", X86CPU, guest_phys_bits, -1),\n DEFINE_PROP_BOOL(\"host-phys-bits\", X86CPU, host_phys_bits, false),\n DEFINE_PROP_UINT8(\"host-phys-bits-limit\", X86CPU, host_phys_bits_limit, 0),\n- DEFINE_PROP_BOOL(\"fill-mtrr-mask\", X86CPU, fill_mtrr_mask, true),\n+ DEFINE_PROP_BOOL(\"fill-mtrr-mask\", X86CPU, fill_mtrr_mask, true,\n+ .flags = OBJ_PROP_FLAG_DEPRECATED),\n DEFINE_PROP_UINT32(\"level-func7\", X86CPU, env.cpuid_level_func7,\n UINT32_MAX),\n DEFINE_PROP_UINT32(\"level\", X86CPU, env.cpuid_level, UINT32_MAX),\n", "prefixes": [ "v2", "15/21" ] }