Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2194831/?format=api
{ "id": 2194831, "url": "http://patchwork.ozlabs.org/api/patches/2194831/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-5-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210023040.3507338-5-gaosong@loongson.cn>", "list_archive_url": null, "date": "2026-02-10T02:30:37", "name": "[PULL,4/7] target/loongarch: Add estimated reciprocal instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c91df4421eaea316caf91d4f631f6e0bf7b20461", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-5-gaosong@loongson.cn/mbox/", "series": [ { "id": 491593, "url": "http://patchwork.ozlabs.org/api/series/491593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491593", "date": "2026-02-10T02:30:38", "name": "[PULL,1/7] target/loongarch: Require atomics to be aligned", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194831/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194831/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95p41fXGz1xtV\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 13:57:32 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpdv0-0002Sm-EQ; Mon, 09 Feb 2026 21:56:02 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1vpduy-0002RZ-Ma\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:56:00 -0500", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1vpduv-0003xN-4U\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:56:00 -0500", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8DxvsM2noppg0oRAA--.55424S3;\n Tue, 10 Feb 2026 10:55:50 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJDxD8Mtnoppm59DAA--.61278S6;\n Tue, 10 Feb 2026 10:55:50 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Jiajie Chen <c@jia.je>,\n\tRichard Henderson <richard.henderson@linaro.org>", "Subject": "[PULL 4/7] target/loongarch: Add estimated reciprocal instructions", "Date": "Tue, 10 Feb 2026 10:30:37 +0800", "Message-Id": "<20260210023040.3507338-5-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20260210023040.3507338-1-gaosong@loongson.cn>", "References": "<20260210023040.3507338-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxD8Mtnoppm59DAA--.61278S6", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nAdd the following new instructions in LoongArch v1.1:\n\n- frecipe.s\n- frecipe.d\n- frsqrte.s\n- frsqrte.d\n- vfrecipe.s\n- vfrecipe.d\n- vfrsqrte.s\n- vfrsqrte.d\n- xvfrecipe.s\n- xvfrecipe.d\n- xvfrsqrte.s\n- xvfrsqrte.d\n\nThey are guarded by CPUCFG2.FRECIPE. Altought the instructions allow\nimplementation to improve performance by reducing precision, we use the\nexisting softfloat implementation.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nAcked-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Song Gao <gaosong@loongson.cn>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\n---\n target/loongarch/cpu.h | 1 +\n target/loongarch/disas.c | 12 ++++++++++++\n target/loongarch/insns.decode | 12 ++++++++++++\n target/loongarch/tcg/insn_trans/trans_farith.c.inc | 4 ++++\n target/loongarch/tcg/insn_trans/trans_vec.c.inc | 8 ++++++++\n target/loongarch/translate.h | 6 ++++++\n 6 files changed, 43 insertions(+)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex a518541c54..8648d0514a 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -138,6 +138,7 @@ FIELD(CPUCFG2, LBT_ALL, 18, 3)\n FIELD(CPUCFG2, LSPW, 21, 1)\n FIELD(CPUCFG2, LAM, 22, 1)\n FIELD(CPUCFG2, HPTW, 24, 1)\n+FIELD(CPUCFG2, FRECIPE, 25, 1)\n FIELD(CPUCFG2, LAM_BH, 27, 1)\n FIELD(CPUCFG2, LAMCAS, 28, 1)\n \ndiff --git a/target/loongarch/disas.c b/target/loongarch/disas.c\nindex 66c0cae5a9..e5e1b37ce0 100644\n--- a/target/loongarch/disas.c\n+++ b/target/loongarch/disas.c\n@@ -478,6 +478,10 @@ INSN(frecip_s, ff)\n INSN(frecip_d, ff)\n INSN(frsqrt_s, ff)\n INSN(frsqrt_d, ff)\n+INSN(frecipe_s, ff)\n+INSN(frecipe_d, ff)\n+INSN(frsqrte_s, ff)\n+INSN(frsqrte_d, ff)\n INSN(fmov_s, ff)\n INSN(fmov_d, ff)\n INSN(movgr2fr_w, fr)\n@@ -1429,6 +1433,10 @@ INSN_LSX(vfrecip_s, vv)\n INSN_LSX(vfrecip_d, vv)\n INSN_LSX(vfrsqrt_s, vv)\n INSN_LSX(vfrsqrt_d, vv)\n+INSN_LSX(vfrecipe_s, vv)\n+INSN_LSX(vfrecipe_d, vv)\n+INSN_LSX(vfrsqrte_s, vv)\n+INSN_LSX(vfrsqrte_d, vv)\n \n INSN_LSX(vfcvtl_s_h, vv)\n INSN_LSX(vfcvth_s_h, vv)\n@@ -2343,6 +2351,10 @@ INSN_LASX(xvfrecip_s, vv)\n INSN_LASX(xvfrecip_d, vv)\n INSN_LASX(xvfrsqrt_s, vv)\n INSN_LASX(xvfrsqrt_d, vv)\n+INSN_LASX(xvfrecipe_s, vv)\n+INSN_LASX(xvfrecipe_d, vv)\n+INSN_LASX(xvfrsqrte_s, vv)\n+INSN_LASX(xvfrsqrte_d, vv)\n \n INSN_LASX(xvfcvtl_s_h, vv)\n INSN_LASX(xvfcvth_s_h, vv)\ndiff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode\nindex cf4123cd46..92078f0f9f 100644\n--- a/target/loongarch/insns.decode\n+++ b/target/loongarch/insns.decode\n@@ -371,6 +371,10 @@ frecip_s 0000 00010001 01000 10101 ..... ..... @ff\n frecip_d 0000 00010001 01000 10110 ..... ..... @ff\n frsqrt_s 0000 00010001 01000 11001 ..... ..... @ff\n frsqrt_d 0000 00010001 01000 11010 ..... ..... @ff\n+frecipe_s 0000 00010001 01000 11101 ..... ..... @ff\n+frecipe_d 0000 00010001 01000 11110 ..... ..... @ff\n+frsqrte_s 0000 00010001 01001 00001 ..... ..... @ff\n+frsqrte_d 0000 00010001 01001 00010 ..... ..... @ff\n fscaleb_s 0000 00010001 00001 ..... ..... ..... @fff\n fscaleb_d 0000 00010001 00010 ..... ..... ..... @fff\n flogb_s 0000 00010001 01000 01001 ..... ..... @ff\n@@ -1115,6 +1119,10 @@ vfrecip_s 0111 00101001 11001 11101 ..... ..... @vv\n vfrecip_d 0111 00101001 11001 11110 ..... ..... @vv\n vfrsqrt_s 0111 00101001 11010 00001 ..... ..... @vv\n vfrsqrt_d 0111 00101001 11010 00010 ..... ..... @vv\n+vfrecipe_s 0111 00101001 11010 00101 ..... ..... @vv\n+vfrecipe_d 0111 00101001 11010 00110 ..... ..... @vv\n+vfrsqrte_s 0111 00101001 11010 01001 ..... ..... @vv\n+vfrsqrte_d 0111 00101001 11010 01010 ..... ..... @vv\n \n vfcvtl_s_h 0111 00101001 11011 11010 ..... ..... @vv\n vfcvth_s_h 0111 00101001 11011 11011 ..... ..... @vv\n@@ -1879,6 +1887,10 @@ xvfrecip_s 0111 01101001 11001 11101 ..... ..... @vv\n xvfrecip_d 0111 01101001 11001 11110 ..... ..... @vv\n xvfrsqrt_s 0111 01101001 11010 00001 ..... ..... @vv\n xvfrsqrt_d 0111 01101001 11010 00010 ..... ..... @vv\n+xvfrecipe_s 0111 01101001 11010 00101 ..... ..... @vv\n+xvfrecipe_d 0111 01101001 11010 00110 ..... ..... @vv\n+xvfrsqrte_s 0111 01101001 11010 01001 ..... ..... @vv\n+xvfrsqrte_d 0111 01101001 11010 01010 ..... ..... @vv\n \n xvfcvtl_s_h 0111 01101001 11011 11010 ..... ..... @vv\n xvfcvth_s_h 0111 01101001 11011 11011 ..... ..... @vv\ndiff --git a/target/loongarch/tcg/insn_trans/trans_farith.c.inc b/target/loongarch/tcg/insn_trans/trans_farith.c.inc\nindex ff6cf3448e..eed6ab7312 100644\n--- a/target/loongarch/tcg/insn_trans/trans_farith.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_farith.c.inc\n@@ -191,6 +191,10 @@ TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s)\n TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d)\n TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s)\n TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d)\n+TRANS(frecipe_s, FRECIPE_FP_SP, gen_ff, gen_helper_frecip_s)\n+TRANS(frecipe_d, FRECIPE_FP_DP, gen_ff, gen_helper_frecip_d)\n+TRANS(frsqrte_s, FRECIPE_FP_SP, gen_ff, gen_helper_frsqrt_s)\n+TRANS(frsqrte_d, FRECIPE_FP_DP, gen_ff, gen_helper_frsqrt_d)\n TRANS64(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s)\n TRANS64(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d)\n TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s)\ndiff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc\nindex ea7e705bab..195b89f788 100644\n--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc\n@@ -4407,12 +4407,20 @@ TRANS(vfrecip_s, LSX, gen_vv_ptr, gen_helper_vfrecip_s)\n TRANS(vfrecip_d, LSX, gen_vv_ptr, gen_helper_vfrecip_d)\n TRANS(vfrsqrt_s, LSX, gen_vv_ptr, gen_helper_vfrsqrt_s)\n TRANS(vfrsqrt_d, LSX, gen_vv_ptr, gen_helper_vfrsqrt_d)\n+TRANS(vfrecipe_s, FRECIPE_LSX, gen_vv_ptr, gen_helper_vfrecip_s)\n+TRANS(vfrecipe_d, FRECIPE_LSX, gen_vv_ptr, gen_helper_vfrecip_d)\n+TRANS(vfrsqrte_s, FRECIPE_LSX, gen_vv_ptr, gen_helper_vfrsqrt_s)\n+TRANS(vfrsqrte_d, FRECIPE_LSX, gen_vv_ptr, gen_helper_vfrsqrt_d)\n TRANS(xvfsqrt_s, LASX, gen_xx_ptr, gen_helper_vfsqrt_s)\n TRANS(xvfsqrt_d, LASX, gen_xx_ptr, gen_helper_vfsqrt_d)\n TRANS(xvfrecip_s, LASX, gen_xx_ptr, gen_helper_vfrecip_s)\n TRANS(xvfrecip_d, LASX, gen_xx_ptr, gen_helper_vfrecip_d)\n TRANS(xvfrsqrt_s, LASX, gen_xx_ptr, gen_helper_vfrsqrt_s)\n TRANS(xvfrsqrt_d, LASX, gen_xx_ptr, gen_helper_vfrsqrt_d)\n+TRANS(xvfrecipe_s, FRECIPE_LASX, gen_xx_ptr, gen_helper_vfrecip_s)\n+TRANS(xvfrecipe_d, FRECIPE_LASX, gen_xx_ptr, gen_helper_vfrecip_d)\n+TRANS(xvfrsqrte_s, FRECIPE_LASX, gen_xx_ptr, gen_helper_vfrsqrt_s)\n+TRANS(xvfrsqrte_d, FRECIPE_LASX, gen_xx_ptr, gen_helper_vfrsqrt_d)\n \n TRANS(vfcvtl_s_h, LSX, gen_vv_ptr, gen_helper_vfcvtl_s_h)\n TRANS(vfcvth_s_h, LSX, gen_vv_ptr, gen_helper_vfcvth_s_h)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 9ba3b425c1..331f79c8f2 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -33,6 +33,12 @@\n #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))\n #define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))\n \n+#define avail_FRECIPE(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FRECIPE))\n+#define avail_FRECIPE_FP_SP(C) (avail_FRECIPE(C) && avail_FP_SP(C))\n+#define avail_FRECIPE_FP_DP(C) (avail_FRECIPE(C) && avail_FP_DP(C))\n+#define avail_FRECIPE_LSX(C) (avail_FRECIPE(C) && avail_LSX(C))\n+#define avail_FRECIPE_LASX(C) (avail_FRECIPE(C) && avail_LASX(C))\n+\n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n * it may require the inputs to be sign- or zero-extended; which will\n", "prefixes": [ "PULL", "4/7" ] }