Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2194828/?format=api
{ "id": 2194828, "url": "http://patchwork.ozlabs.org/api/patches/2194828/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-7-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210023040.3507338-7-gaosong@loongson.cn>", "list_archive_url": null, "date": "2026-02-10T02:30:39", "name": "[PULL,6/7] target/loongarch: Add sc.q instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "38d2caa9d911a3857209797b3a17ba3ddf52c428", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-7-gaosong@loongson.cn/mbox/", "series": [ { "id": 491593, "url": "http://patchwork.ozlabs.org/api/series/491593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491593", "date": "2026-02-10T02:30:38", "name": "[PULL,1/7] target/loongarch: Require atomics to be aligned", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194828/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194828/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95nY3llsz1xwG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 13:57:05 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpdv2-0002TH-C9; Mon, 09 Feb 2026 21:56:04 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1vpduz-0002Rt-6G\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:56:01 -0500", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1vpduv-0003xV-OG\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:56:00 -0500", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8BxcfA4nopph0oRAA--.55718S3;\n Tue, 10 Feb 2026 10:55:52 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJDxD8Mtnoppm59DAA--.61278S8;\n Tue, 10 Feb 2026 10:55:51 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Jiajie Chen <c@jia.je>", "Subject": "[PULL 6/7] target/loongarch: Add sc.q instructions", "Date": "Tue, 10 Feb 2026 10:30:39 +0800", "Message-Id": "<20260210023040.3507338-7-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20260210023040.3507338-1-gaosong@loongson.cn>", "References": "<20260210023040.3507338-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxD8Mtnoppm59DAA--.61278S8", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nAdd the sc.q instruction in LoongArch v1.1, guarded by CPUCFG2.SCQ. It\nis implemented by reading 128bit data (llval + llval_high) in ll.d when\naligned to 16B boundary, and cmpxchg 128bit in sc.q. If ld.d\nmatches the higher part of the 128bit, its data is taken from\nllval_high.\n\nExpected assembly sequence:\n\nll.d lo, base, 0\nld.d hi, base, 8\nsc.q lo, hi, base\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nReviewed-by: Song Gao <gaosong@loongson.cn>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\n---\n target/loongarch/cpu.h | 3 +\n target/loongarch/disas.c | 1 +\n target/loongarch/insns.decode | 1 +\n .../tcg/insn_trans/trans_atomic.c.inc | 82 +++++++++++++++++++\n .../tcg/insn_trans/trans_memory.c.inc | 22 +++++\n target/loongarch/tcg/translate.c | 6 +-\n target/loongarch/translate.h | 1 +\n 7 files changed, 115 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex 77080091fe..8c198fa584 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -142,6 +142,7 @@ FIELD(CPUCFG2, FRECIPE, 25, 1)\n FIELD(CPUCFG2, LAM_BH, 27, 1)\n FIELD(CPUCFG2, LAMCAS, 28, 1)\n FIELD(CPUCFG2, LLACQ_SCREL, 29, 1)\n+FIELD(CPUCFG2, SCQ, 30, 1)\n \n /* cpucfg[3] bits */\n FIELD(CPUCFG3, CCDMA, 0, 1)\n@@ -381,6 +382,8 @@ typedef struct CPUArchState {\n uint32_t fcsr0_mask;\n uint64_t lladdr; /* LL virtual address compared against SC */\n uint64_t llval;\n+ uint64_t llval_high; /* For 128-bit atomic SC.Q */\n+ uint64_t llbit_scq; /* Potential LL.D+LD.D+SC.Q sequence in effect */\n #endif\n #ifndef CONFIG_USER_ONLY\n #ifdef CONFIG_TCG\ndiff --git a/target/loongarch/disas.c b/target/loongarch/disas.c\nindex 3164fade9b..3249ab7ac6 100644\n--- a/target/loongarch/disas.c\n+++ b/target/loongarch/disas.c\n@@ -584,6 +584,7 @@ INSN(fldx_s, frr)\n INSN(fldx_d, frr)\n INSN(fstx_s, frr)\n INSN(fstx_d, frr)\n+INSN(sc_q, rrr)\n INSN(llacq_w, rr_i)\n INSN(screl_w, rr_i)\n INSN(llacq_d, rr_i)\ndiff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode\nindex 7898f5f719..3089d42044 100644\n--- a/target/loongarch/insns.decode\n+++ b/target/loongarch/insns.decode\n@@ -262,6 +262,7 @@ ll_w 0010 0000 .............. ..... ..... @rr_i14s2\n sc_w 0010 0001 .............. ..... ..... @rr_i14s2\n ll_d 0010 0010 .............. ..... ..... @rr_i14s2\n sc_d 0010 0011 .............. ..... ..... @rr_i14s2\n+sc_q 0011 10000101 01110 ..... ..... ..... @rrr\n llacq_w 0011 10000101 01111 00000 ..... ..... @rr_i0\n screl_w 0011 10000101 01111 00001 ..... ..... @rr_i0\n llacq_d 0011 10000101 01111 00010 ..... ..... @rr_i0\ndiff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\nindex a294c5dd52..4bf8dab780 100644\n--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n@@ -6,14 +6,48 @@\n static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool acq)\n {\n TCGv t1 = tcg_temp_new();\n+ TCGv t2 = tcg_temp_new();\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n TCGv t0 = make_address_i(ctx, src1, a->imm);\n+ TCGv_i128 t16 = tcg_temp_new_i128();\n+ TCGv mask = tcg_constant_tl(0xf);\n+ TCGv one = tcg_constant_tl(1);\n+ TCGv zero = tcg_constant_tl(0);\n+ TCGLabel *l1 = gen_new_label();\n+ TCGLabel *done = gen_new_label();\n+\n+ if (avail_SCQ(ctx) && mop == MO_LEUQ) {\n+ /*\n+ * The LL.D+LD.D may be paired with SC.Q,\n+ * load 128-bit if aligned: (t0 & 0xf) == 0\n+ */\n+ tcg_gen_and_tl(t1, t0, mask);\n+ tcg_gen_brcond_tl(TCG_COND_EQ, t1, zero, l1);\n+ /* fallthrough if not aligned to 16B */\n+ }\n \n tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop | MO_ALIGN);\n tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));\n tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));\n gen_set_gpr(a->rd, t1, EXT_NONE);\n \n+ if (avail_SCQ(ctx) && mop == MO_LEUQ) {\n+ tcg_gen_br(done);\n+\n+ gen_set_label(l1);\n+\n+ /* Load 16B data and save into llval/llval_high */\n+ tcg_gen_qemu_ld_i128(t16, t0, ctx->mem_idx, MO_128 | MO_ALIGN);\n+ tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));\n+ tcg_gen_extr_i128_i64(t1, t2, t16);\n+ tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));\n+ tcg_gen_st_tl(t2, tcg_env, offsetof(CPULoongArchState, llval_high));\n+ tcg_gen_st_tl(one, tcg_env, offsetof(CPULoongArchState, llbit_scq));\n+ gen_set_gpr(a->rd, t1, EXT_NONE);\n+\n+ gen_set_label(done);\n+ }\n+\n if (acq) {\n tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);\n }\n@@ -28,6 +62,7 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel)\n TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);\n TCGv t0 = tcg_temp_new();\n TCGv val = tcg_temp_new();\n+ TCGv zero = tcg_constant_tl(0);\n \n TCGLabel *l1 = gen_new_label();\n TCGLabel *done = gen_new_label();\n@@ -37,6 +72,11 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel)\n if (rel) {\n tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);\n }\n+\n+ if (avail_SCQ(ctx)) {\n+ tcg_gen_st_tl(zero, tcg_env, offsetof(CPULoongArchState, llbit_scq));\n+ }\n+\n tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);\n tcg_gen_movi_tl(dest, 0);\n tcg_gen_br(done);\n@@ -53,6 +93,47 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel)\n return true;\n }\n \n+static bool gen_sc_q(DisasContext *ctx, arg_rrr *a, MemOp mop)\n+{\n+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n+ TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);\n+ TCGv src3 = gpr_src(ctx, a->rk, EXT_NONE);\n+ TCGv_i128 t16 = tcg_temp_new_i128();\n+ TCGv_i128 c16 = tcg_temp_new_i128();\n+ TCGv t1 = tcg_temp_new();\n+ TCGv t2 = tcg_temp_new();\n+ TCGv zero = tcg_constant_tl(0);\n+\n+ TCGLabel *l1 = gen_new_label();\n+ TCGLabel *done = gen_new_label();\n+\n+ tcg_gen_st_tl(zero, tcg_env, offsetof(CPULoongArchState, llbit_scq));\n+ tcg_gen_brcond_tl(TCG_COND_EQ, src1, cpu_lladdr, l1);\n+ tcg_gen_movi_tl(dest, 0);\n+ tcg_gen_br(done);\n+\n+ gen_set_label(l1);\n+ tcg_gen_concat_i64_i128(t16, src2, src3);\n+ tcg_gen_concat_i64_i128(c16, cpu_llval,\n+ cpu_llval_high);\n+\n+ /* generate cmpxchg */\n+ tcg_gen_atomic_cmpxchg_i128(t16, cpu_lladdr, c16,\n+ t16, ctx->mem_idx, mop | MO_ALIGN);\n+\n+ /* check if success */\n+ tcg_gen_extr_i128_i64(t1, t2, t16);\n+ tcg_gen_xor_i64(t1, t1, cpu_llval);\n+ tcg_gen_xor_i64(t2, t2, cpu_llval_high);\n+ tcg_gen_or_i64(t1, t1, t2);\n+ tcg_gen_setcondi_i64(TCG_COND_EQ, dest, t1, 0);\n+ gen_set_label(done);\n+ gen_set_gpr(a->rd, dest, EXT_NONE);\n+\n+ return true;\n+}\n+\n static bool gen_cas(DisasContext *ctx, arg_rrr *a,\n void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp),\n MemOp mop)\n@@ -98,6 +179,7 @@ TRANS(ll_w, ALL, gen_ll, MO_LESL, false)\n TRANS(sc_w, ALL, gen_sc, MO_LESL, false)\n TRANS(ll_d, 64, gen_ll, MO_LEUQ, false)\n TRANS(sc_d, 64, gen_sc, MO_LEUQ, false)\n+TRANS(sc_q, 64, gen_sc_q, MO_128)\n TRANS(llacq_w, LLACQ_SCREL, gen_ll, MO_LESL, true)\n TRANS(screl_w, LLACQ_SCREL, gen_sc, MO_LESL, true)\n TRANS(llacq_d, LLACQ_SCREL_64, gen_ll, MO_LEUQ, true)\ndiff --git a/target/loongarch/tcg/insn_trans/trans_memory.c.inc b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\nindex 90bb0815ff..e287d46363 100644\n--- a/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_memory.c.inc\n@@ -7,11 +7,33 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n {\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n+ TCGv t1 = tcg_temp_new();\n+ TCGv mask = tcg_constant_tl(0x8);\n+ TCGv zero = tcg_constant_tl(0);\n+ TCGLabel *done = gen_new_label();\n+ TCGLabel *l1 = gen_new_label();\n \n addr = make_address_i(ctx, addr, a->imm);\n \n+ if (avail_SCQ(ctx) && mop == MO_LEUQ) {\n+ /*\n+ * The LL.D+LD.D may be paired with SC.Q,\n+ * use llval_high if llbit_scq && (addr == lladdr ^ 0x8)\n+ */\n+ tcg_gen_brcond_tl(TCG_COND_EQ, cpu_llbit_scq, zero, l1);\n+ tcg_gen_xor_tl(t1, addr, mask);\n+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_lladdr, t1, l1);\n+ gen_set_gpr(a->rd, cpu_llval_high, EXT_NONE);\n+ tcg_gen_br(done);\n+ gen_set_label(l1);\n+ }\n+\n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n+\n+ if (avail_SCQ(ctx) && mop == MO_LEUQ) {\n+ gen_set_label(done);\n+ }\n return true;\n }\n \ndiff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c\nindex c23d2a614a..30f375b33f 100644\n--- a/target/loongarch/tcg/translate.c\n+++ b/target/loongarch/tcg/translate.c\n@@ -24,7 +24,7 @@\n \n /* Global register indices */\n TCGv cpu_gpr[32], cpu_pc;\n-static TCGv cpu_lladdr, cpu_llval;\n+static TCGv cpu_lladdr, cpu_llval, cpu_llval_high, cpu_llbit_scq;\n \n #define HELPER_H \"helper.h\"\n #include \"exec/helper-info.c.inc\"\n@@ -361,6 +361,10 @@ void loongarch_translate_init(void)\n offsetof(CPULoongArchState, lladdr), \"lladdr\");\n cpu_llval = tcg_global_mem_new(tcg_env,\n offsetof(CPULoongArchState, llval), \"llval\");\n+ cpu_llval_high = tcg_global_mem_new(tcg_env,\n+ offsetof(CPULoongArchState, llval_high), \"llval_high\");\n+ cpu_llbit_scq = tcg_global_mem_new(tcg_env,\n+ offsetof(CPULoongArchState, llbit_scq), \"llbit_scq\");\n \n #ifndef CONFIG_USER_ONLY\n loongarch_csr_translate_init();\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 76bceedf98..ba1c89e57b 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -30,6 +30,7 @@\n #define avail_LAMCAS(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAMCAS))\n #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))\n #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))\n+#define avail_SCQ(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, SCQ))\n #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))\n #define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))\n \n", "prefixes": [ "PULL", "6/7" ] }