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GET /api/patches/2194827/?format=api
{ "id": 2194827, "url": "http://patchwork.ozlabs.org/api/patches/2194827/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-4-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210023040.3507338-4-gaosong@loongson.cn>", "list_archive_url": null, "date": "2026-02-10T02:30:36", "name": "[PULL,3/7] target/loongarch: Add amcas[_db].{b/h/w/d}", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "97062309ef72b5988cfb1c371042f740bf3daa0e", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-4-gaosong@loongson.cn/mbox/", "series": [ { "id": 491593, "url": "http://patchwork.ozlabs.org/api/series/491593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491593", "date": "2026-02-10T02:30:38", "name": "[PULL,1/7] target/loongarch: Require atomics to be aligned", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194827/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194827/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95nT1bzbz1xwG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 13:57:01 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpduz-0002RC-9J; Mon, 09 Feb 2026 21:56:01 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1vpdux-0002QG-4J\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:59 -0500", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1vpdut-0003wn-Of\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:58 -0500", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8AxjsM2noppf0oRAA--.55777S3;\n Tue, 10 Feb 2026 10:55:50 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJDxD8Mtnoppm59DAA--.61278S5;\n Tue, 10 Feb 2026 10:55:49 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Jiajie Chen <c@jia.je>", "Subject": "[PULL 3/7] target/loongarch: Add amcas[_db].{b/h/w/d}", "Date": "Tue, 10 Feb 2026 10:30:36 +0800", "Message-Id": "<20260210023040.3507338-4-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20260210023040.3507338-1-gaosong@loongson.cn>", "References": "<20260210023040.3507338-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxD8Mtnoppm59DAA--.61278S5", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nThe new instructions are introduced in LoongArch v1.1:\n\n- amcas.b\n- amcas.h\n- amcas.w\n- amcas.d\n- amcas_db.b\n- amcas_db.h\n- amcas_db.w\n- amcas_db.d\n\nThe new instructions are gated by CPUCFG2.LAMCAS.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nReviewed-by: Song Gao <gaosong@loongson.cn>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\n---\n target/loongarch/cpu.h | 1 +\n target/loongarch/disas.c | 8 ++++++\n target/loongarch/insns.decode | 8 ++++++\n .../tcg/insn_trans/trans_atomic.c.inc | 25 +++++++++++++++++++\n target/loongarch/translate.h | 1 +\n 5 files changed, 43 insertions(+)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex 013525bf45..a518541c54 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -139,6 +139,7 @@ FIELD(CPUCFG2, LSPW, 21, 1)\n FIELD(CPUCFG2, LAM, 22, 1)\n FIELD(CPUCFG2, HPTW, 24, 1)\n FIELD(CPUCFG2, LAM_BH, 27, 1)\n+FIELD(CPUCFG2, LAMCAS, 28, 1)\n \n /* cpucfg[3] bits */\n FIELD(CPUCFG3, CCDMA, 0, 1)\ndiff --git a/target/loongarch/disas.c b/target/loongarch/disas.c\nindex 1a0f527cb1..66c0cae5a9 100644\n--- a/target/loongarch/disas.c\n+++ b/target/loongarch/disas.c\n@@ -580,6 +580,14 @@ INSN(fldx_s, frr)\n INSN(fldx_d, frr)\n INSN(fstx_s, frr)\n INSN(fstx_d, frr)\n+INSN(amcas_b, rrr)\n+INSN(amcas_h, rrr)\n+INSN(amcas_w, rrr)\n+INSN(amcas_d, rrr)\n+INSN(amcas_db_b, rrr)\n+INSN(amcas_db_h, rrr)\n+INSN(amcas_db_w, rrr)\n+INSN(amcas_db_d, rrr)\n INSN(amswap_b, rrr)\n INSN(amswap_h, rrr)\n INSN(amadd_b, rrr)\ndiff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode\nindex 678ce42038..cf4123cd46 100644\n--- a/target/loongarch/insns.decode\n+++ b/target/loongarch/insns.decode\n@@ -261,6 +261,14 @@ ll_w 0010 0000 .............. ..... ..... @rr_i14s2\n sc_w 0010 0001 .............. ..... ..... @rr_i14s2\n ll_d 0010 0010 .............. ..... ..... @rr_i14s2\n sc_d 0010 0011 .............. ..... ..... @rr_i14s2\n+amcas_b 0011 10000101 10000 ..... ..... ..... @rrr\n+amcas_h 0011 10000101 10001 ..... ..... ..... @rrr\n+amcas_w 0011 10000101 10010 ..... ..... ..... @rrr\n+amcas_d 0011 10000101 10011 ..... ..... ..... @rrr\n+amcas_db_b 0011 10000101 10100 ..... ..... ..... @rrr\n+amcas_db_h 0011 10000101 10101 ..... ..... ..... @rrr\n+amcas_db_w 0011 10000101 10110 ..... ..... ..... @rrr\n+amcas_db_d 0011 10000101 10111 ..... ..... ..... @rrr\n amswap_b 0011 10000101 11000 ..... ..... ..... @rrr\n amswap_h 0011 10000101 11001 ..... ..... ..... @rrr\n amadd_b 0011 10000101 11010 ..... ..... ..... @rrr\ndiff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\nindex 17e72bab47..b27c91a927 100644\n--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n@@ -45,6 +45,23 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n return true;\n }\n \n+static bool gen_cas(DisasContext *ctx, arg_rrr *a,\n+ void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp),\n+ MemOp mop)\n+{\n+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n+ TCGv val = gpr_src(ctx, a->rk, EXT_NONE);\n+ TCGv old = gpr_src(ctx, a->rd, EXT_NONE);\n+\n+ addr = make_address_i(ctx, addr, 0);\n+\n+ func(dest, addr, old, val, ctx->mem_idx, mop | MO_ALIGN);\n+ gen_set_gpr(a->rd, dest, EXT_NONE);\n+\n+ return true;\n+}\n+\n static bool gen_am(DisasContext *ctx, arg_rrr *a,\n void (*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),\n MemOp mop)\n@@ -73,6 +90,14 @@ TRANS(ll_w, ALL, gen_ll, MO_LESL)\n TRANS(sc_w, ALL, gen_sc, MO_LESL)\n TRANS(ll_d, 64, gen_ll, MO_LEUQ)\n TRANS(sc_d, 64, gen_sc, MO_LEUQ)\n+TRANS(amcas_b, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_SB)\n+TRANS(amcas_h, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESW)\n+TRANS(amcas_w, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESL)\n+TRANS(amcas_d, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LEUQ)\n+TRANS(amcas_db_b, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_SB)\n+TRANS(amcas_db_h, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESW)\n+TRANS(amcas_db_w, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESL)\n+TRANS(amcas_db_d, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LEUQ)\n TRANS(amswap_b, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_SB)\n TRANS(amswap_h, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_LESW)\n TRANS(amadd_b, LAM_BH, gen_am, tcg_gen_atomic_fetch_add_tl, MO_SB)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex eb424bb0da..9ba3b425c1 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -27,6 +27,7 @@\n #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))\n #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))\n #define avail_LAM_BH(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM_BH))\n+#define avail_LAMCAS(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAMCAS))\n #define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))\n #define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))\n #define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))\n", "prefixes": [ "PULL", "3/7" ] }