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GET /api/patches/2194825/?format=api
{ "id": 2194825, "url": "http://patchwork.ozlabs.org/api/patches/2194825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-3-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210023040.3507338-3-gaosong@loongson.cn>", "list_archive_url": null, "date": "2026-02-10T02:30:35", "name": "[PULL,2/7] target/loongarch: Add am{swap/add}[_db].{b/h}", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b26d4d8f7e35bd3ef25be0eb78be319022c4864", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-3-gaosong@loongson.cn/mbox/", "series": [ { "id": 491593, "url": "http://patchwork.ozlabs.org/api/series/491593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491593", "date": "2026-02-10T02:30:38", "name": "[PULL,1/7] target/loongarch: Require atomics to be aligned", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194825/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95nM6nPSz1xwG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 13:56:55 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpdv0-0002Sn-TB; Mon, 09 Feb 2026 21:56:02 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1vpdux-0002Qh-IP\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:59 -0500", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1vpduu-0003x0-EA\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:59 -0500", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8Axz8M1noppfUoRAA--.55629S3;\n Tue, 10 Feb 2026 10:55:49 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJDxD8Mtnoppm59DAA--.61278S4;\n Tue, 10 Feb 2026 10:55:49 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Jiajie Chen <c@jia.je>,\n\tRichard Henderson <richard.henderson@linaro.org>", "Subject": "[PULL 2/7] target/loongarch: Add am{swap/add}[_db].{b/h}", "Date": "Tue, 10 Feb 2026 10:30:35 +0800", "Message-Id": "<20260210023040.3507338-3-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20260210023040.3507338-1-gaosong@loongson.cn>", "References": "<20260210023040.3507338-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxD8Mtnoppm59DAA--.61278S4", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nThe new instructions are introduced in LoongArch v1.1:\n\n- amswap.b\n- amswap.h\n- amadd.b\n- amadd.h\n- amswap_db.b\n- amswap_db.h\n- amadd_db.b\n- amadd_db.h\n\nThe instructions are gated by CPUCFG2.LAM_BH.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Song Gao <gaosong@loongson.cn>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\n---\n target/loongarch/cpu.h | 1 +\n target/loongarch/disas.c | 8 ++++++++\n target/loongarch/insns.decode | 8 ++++++++\n .../tcg/insn_trans/trans_atomic.c.inc | 8 ++++++++\n target/loongarch/translate.h | 19 ++++++++++---------\n 5 files changed, 35 insertions(+), 9 deletions(-)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex 0485cdbda0..013525bf45 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -138,6 +138,7 @@ FIELD(CPUCFG2, LBT_ALL, 18, 3)\n FIELD(CPUCFG2, LSPW, 21, 1)\n FIELD(CPUCFG2, LAM, 22, 1)\n FIELD(CPUCFG2, HPTW, 24, 1)\n+FIELD(CPUCFG2, LAM_BH, 27, 1)\n \n /* cpucfg[3] bits */\n FIELD(CPUCFG3, CCDMA, 0, 1)\ndiff --git a/target/loongarch/disas.c b/target/loongarch/disas.c\nindex 63989a6282..1a0f527cb1 100644\n--- a/target/loongarch/disas.c\n+++ b/target/loongarch/disas.c\n@@ -580,6 +580,14 @@ INSN(fldx_s, frr)\n INSN(fldx_d, frr)\n INSN(fstx_s, frr)\n INSN(fstx_d, frr)\n+INSN(amswap_b, rrr)\n+INSN(amswap_h, rrr)\n+INSN(amadd_b, rrr)\n+INSN(amadd_h, rrr)\n+INSN(amswap_db_b, rrr)\n+INSN(amswap_db_h, rrr)\n+INSN(amadd_db_b, rrr)\n+INSN(amadd_db_h, rrr)\n INSN(amswap_w, rrr)\n INSN(amswap_d, rrr)\n INSN(amadd_w, rrr)\ndiff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode\nindex 62f58cc541..678ce42038 100644\n--- a/target/loongarch/insns.decode\n+++ b/target/loongarch/insns.decode\n@@ -261,6 +261,14 @@ ll_w 0010 0000 .............. ..... ..... @rr_i14s2\n sc_w 0010 0001 .............. ..... ..... @rr_i14s2\n ll_d 0010 0010 .............. ..... ..... @rr_i14s2\n sc_d 0010 0011 .............. ..... ..... @rr_i14s2\n+amswap_b 0011 10000101 11000 ..... ..... ..... @rrr\n+amswap_h 0011 10000101 11001 ..... ..... ..... @rrr\n+amadd_b 0011 10000101 11010 ..... ..... ..... @rrr\n+amadd_h 0011 10000101 11011 ..... ..... ..... @rrr\n+amswap_db_b 0011 10000101 11100 ..... ..... ..... @rrr\n+amswap_db_h 0011 10000101 11101 ..... ..... ..... @rrr\n+amadd_db_b 0011 10000101 11110 ..... ..... ..... @rrr\n+amadd_db_h 0011 10000101 11111 ..... ..... ..... @rrr\n amswap_w 0011 10000110 00000 ..... ..... ..... @rrr\n amswap_d 0011 10000110 00001 ..... ..... ..... @rrr\n amadd_w 0011 10000110 00010 ..... ..... ..... @rrr\ndiff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\nindex b8c962b65a..17e72bab47 100644\n--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n@@ -73,6 +73,14 @@ TRANS(ll_w, ALL, gen_ll, MO_LESL)\n TRANS(sc_w, ALL, gen_sc, MO_LESL)\n TRANS(ll_d, 64, gen_ll, MO_LEUQ)\n TRANS(sc_d, 64, gen_sc, MO_LEUQ)\n+TRANS(amswap_b, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_SB)\n+TRANS(amswap_h, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_LESW)\n+TRANS(amadd_b, LAM_BH, gen_am, tcg_gen_atomic_fetch_add_tl, MO_SB)\n+TRANS(amadd_h, LAM_BH, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LESW)\n+TRANS(amswap_db_b, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_SB)\n+TRANS(amswap_db_h, LAM_BH, gen_am, tcg_gen_atomic_xchg_tl, MO_LESW)\n+TRANS(amadd_db_b, LAM_BH, gen_am, tcg_gen_atomic_fetch_add_tl, MO_SB)\n+TRANS(amadd_db_h, LAM_BH, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LESW)\n TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LESL)\n TRANS64(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_LEUQ)\n TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_LESL)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex bbe015ba57..eb424bb0da 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -21,15 +21,16 @@\n #define avail_ALL(C) true\n #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \\\n CPUCFG1_ARCH_LA64)\n-#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))\n-#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))\n-#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))\n-#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))\n-#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))\n-#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))\n-#define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))\n-#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))\n-#define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))\n+#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))\n+#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))\n+#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))\n+#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))\n+#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))\n+#define avail_LAM_BH(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM_BH))\n+#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))\n+#define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))\n+#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))\n+#define avail_CRC(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, CRC))\n \n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n", "prefixes": [ "PULL", "2/7" ] }