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GET /api/patches/2194824/?format=api
{ "id": 2194824, "url": "http://patchwork.ozlabs.org/api/patches/2194824/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-6-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210023040.3507338-6-gaosong@loongson.cn>", "list_archive_url": null, "date": "2026-02-10T02:30:38", "name": "[PULL,5/7] target/loongarch: Add llacq/screl instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1d494708106c1036756977cfae81cfb3140a4915", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260210023040.3507338-6-gaosong@loongson.cn/mbox/", "series": [ { "id": 491593, "url": "http://patchwork.ozlabs.org/api/series/491593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491593", "date": "2026-02-10T02:30:38", "name": "[PULL,1/7] target/loongarch: Require atomics to be aligned", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194824/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194824/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4f95nH32w5z1xwG\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 10 Feb 2026 13:56:49 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vpduz-0002SY-RK; Mon, 09 Feb 2026 21:56:01 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1vpdux-0002Qe-Gs\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:59 -0500", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1vpduu-0003xG-GJ\n for qemu-devel@nongnu.org; Mon, 09 Feb 2026 21:55:59 -0500", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8Axz8M3nopphkoRAA--.55633S3;\n Tue, 10 Feb 2026 10:55:51 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by front1 (Coremail) with SMTP id qMiowJDxD8Mtnoppm59DAA--.61278S7;\n Tue, 10 Feb 2026 10:55:50 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Jiajie Chen <c@jia.je>,\n\tRichard Henderson <richard.henderson@linaro.org>", "Subject": "[PULL 5/7] target/loongarch: Add llacq/screl instructions", "Date": "Tue, 10 Feb 2026 10:30:38 +0800", "Message-Id": "<20260210023040.3507338-6-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20260210023040.3507338-1-gaosong@loongson.cn>", "References": "<20260210023040.3507338-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qMiowJDxD8Mtnoppm59DAA--.61278S7", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nAdd the following instructions in LoongArch v1.1:\n\n- llacq.w\n- screl.w\n- llacq.d\n- screl.d\n\nThey are guarded by CPUCFG2.LLACQ_SCREL.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nCo-developed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Song Gao <gaosong@loongson.cn>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\n---\n target/loongarch/cpu.h | 1 +\n target/loongarch/disas.c | 4 ++++\n target/loongarch/insns.decode | 5 ++++\n .../tcg/insn_trans/trans_atomic.c.inc | 24 ++++++++++++++-----\n target/loongarch/translate.h | 3 +++\n 5 files changed, 31 insertions(+), 6 deletions(-)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex 8648d0514a..77080091fe 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -141,6 +141,7 @@ FIELD(CPUCFG2, HPTW, 24, 1)\n FIELD(CPUCFG2, FRECIPE, 25, 1)\n FIELD(CPUCFG2, LAM_BH, 27, 1)\n FIELD(CPUCFG2, LAMCAS, 28, 1)\n+FIELD(CPUCFG2, LLACQ_SCREL, 29, 1)\n \n /* cpucfg[3] bits */\n FIELD(CPUCFG3, CCDMA, 0, 1)\ndiff --git a/target/loongarch/disas.c b/target/loongarch/disas.c\nindex e5e1b37ce0..3164fade9b 100644\n--- a/target/loongarch/disas.c\n+++ b/target/loongarch/disas.c\n@@ -584,6 +584,10 @@ INSN(fldx_s, frr)\n INSN(fldx_d, frr)\n INSN(fstx_s, frr)\n INSN(fstx_d, frr)\n+INSN(llacq_w, rr_i)\n+INSN(screl_w, rr_i)\n+INSN(llacq_d, rr_i)\n+INSN(screl_d, rr_i)\n INSN(amcas_b, rrr)\n INSN(amcas_h, rrr)\n INSN(amcas_w, rrr)\ndiff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode\nindex 92078f0f9f..7898f5f719 100644\n--- a/target/loongarch/insns.decode\n+++ b/target/loongarch/insns.decode\n@@ -69,6 +69,7 @@\n @rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2\n @rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i\n @rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16\n+@rr_i0 .... .. ................ rj:5 rd:5 &rr_i imm=0\n @hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i\n @hint_rr .... ........ ..... rk:5 rj:5 hint:5 &hint_rr\n @rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1\n@@ -261,6 +262,10 @@ ll_w 0010 0000 .............. ..... ..... @rr_i14s2\n sc_w 0010 0001 .............. ..... ..... @rr_i14s2\n ll_d 0010 0010 .............. ..... ..... @rr_i14s2\n sc_d 0010 0011 .............. ..... ..... @rr_i14s2\n+llacq_w 0011 10000101 01111 00000 ..... ..... @rr_i0\n+screl_w 0011 10000101 01111 00001 ..... ..... @rr_i0\n+llacq_d 0011 10000101 01111 00010 ..... ..... @rr_i0\n+screl_d 0011 10000101 01111 00011 ..... ..... @rr_i0\n amcas_b 0011 10000101 10000 ..... ..... ..... @rrr\n amcas_h 0011 10000101 10001 ..... ..... ..... @rrr\n amcas_w 0011 10000101 10010 ..... ..... ..... @rrr\ndiff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\nindex b27c91a927..a294c5dd52 100644\n--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc\n@@ -3,7 +3,7 @@\n * Copyright (c) 2021 Loongson Technology Corporation Limited\n */\n \n-static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n+static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool acq)\n {\n TCGv t1 = tcg_temp_new();\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -14,10 +14,14 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));\n gen_set_gpr(a->rd, t1, EXT_NONE);\n \n+ if (acq) {\n+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);\n+ }\n+\n return true;\n }\n \n-static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n+static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop, bool rel)\n {\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -29,6 +33,10 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TCGLabel *done = gen_new_label();\n \n tcg_gen_addi_tl(t0, src1, a->imm);\n+\n+ if (rel) {\n+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);\n+ }\n tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);\n tcg_gen_movi_tl(dest, 0);\n tcg_gen_br(done);\n@@ -86,10 +94,14 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,\n return true;\n }\n \n-TRANS(ll_w, ALL, gen_ll, MO_LESL)\n-TRANS(sc_w, ALL, gen_sc, MO_LESL)\n-TRANS(ll_d, 64, gen_ll, MO_LEUQ)\n-TRANS(sc_d, 64, gen_sc, MO_LEUQ)\n+TRANS(ll_w, ALL, gen_ll, MO_LESL, false)\n+TRANS(sc_w, ALL, gen_sc, MO_LESL, false)\n+TRANS(ll_d, 64, gen_ll, MO_LEUQ, false)\n+TRANS(sc_d, 64, gen_sc, MO_LEUQ, false)\n+TRANS(llacq_w, LLACQ_SCREL, gen_ll, MO_LESL, true)\n+TRANS(screl_w, LLACQ_SCREL, gen_sc, MO_LESL, true)\n+TRANS(llacq_d, LLACQ_SCREL_64, gen_ll, MO_LEUQ, true)\n+TRANS(screl_d, LLACQ_SCREL_64, gen_sc, MO_LEUQ, true)\n TRANS(amcas_b, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_SB)\n TRANS(amcas_h, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESW)\n TRANS(amcas_w, LAMCAS, gen_cas, tcg_gen_atomic_cmpxchg_tl, MO_LESL)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 331f79c8f2..76bceedf98 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -39,6 +39,9 @@\n #define avail_FRECIPE_LSX(C) (avail_FRECIPE(C) && avail_LSX(C))\n #define avail_FRECIPE_LASX(C) (avail_FRECIPE(C) && avail_LASX(C))\n \n+#define avail_LLACQ_SCREL(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LLACQ_SCREL))\n+#define avail_LLACQ_SCREL_64(C) (avail_64(C) && avail_LLACQ_SCREL(C))\n+\n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n * it may require the inputs to be sign- or zero-extended; which will\n", "prefixes": [ "PULL", "5/7" ] }