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GET /api/patches/2194731/?format=api
{ "id": 2194731, "url": "http://patchwork.ozlabs.org/api/patches/2194731/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260209-mtk-mt8391-initial-support-v1-2-b23ab9d0b9bc@baylibre.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260209-mtk-mt8391-initial-support-v1-2-b23ab9d0b9bc@baylibre.com>", "list_archive_url": null, "date": "2026-02-09T18:23:16", "name": "[2/4] arm: dts: mediatek: Add MediaTek MT8189 dtsi file", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8fc27eb8db5d1c6e0c181b9728e1d81bf626d02a", "submitter": { "id": 87228, "url": "http://patchwork.ozlabs.org/api/people/87228/?format=api", "name": "David Lechner", "email": "dlechner@baylibre.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260209-mtk-mt8391-initial-support-v1-2-b23ab9d0b9bc@baylibre.com/mbox/", "series": [ { "id": 491550, "url": "http://patchwork.ozlabs.org/api/series/491550/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491550", "date": "2026-02-09T18:23:14", "name": "boards: mediatek: initial support for Genio 720 EVK", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491550/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194731/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=baylibre-com.20230601.gappssmtp.com\n header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=wMOrT8+x;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260209-mtk-mt8391-initial-support-v1-2-b23ab9d0b9bc@baylibre.com>", "References": "\n <20260209-mtk-mt8391-initial-support-v1-0-b23ab9d0b9bc@baylibre.com>", "In-Reply-To": "\n <20260209-mtk-mt8391-initial-support-v1-0-b23ab9d0b9bc@baylibre.com>", "To": "Tom Rini <trini@konsulko.com>, Ryder Lee <ryder.lee@mediatek.com>,\n Weijie Gao <weijie.gao@mediatek.com>,\n Chunfeng Yun <chunfeng.yun@mediatek.com>,\n Igor Belwon <igor.belwon@mentallysanemainliners.org>,\n GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,\n Macpaul Lin <macpaul.lin@mediatek.com>", "Cc": "Julien Stephan <jstephan@baylibre.com>, u-boot@lists.denx.de,\n David Lechner <dlechner@baylibre.com>,\n Chris-QJ Chen <chris-qj.chen@mediatek.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=6181; i=dlechner@baylibre.com;\n h=from:subject:message-id;\n bh=xCpjDx1IEmWZG/ufmbkSHBjqiu9Xe07a90z2kan2oxE=;\n b=owEBhAF7/pANAwAKAcLMIAH/AY/AAcsmYgBpiiYrBhZRbZIIWGXfb7QjElLSBos6crAiIjalw\n 0d54g0+L6WJAUoEAAEKADQWIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaYomKxYcZGxlY2huZXJA\n YmF5bGlicmUuY29tAAoJEMLMIAH/AY/A0SUIAIsIrusAfrR9XV1GOI/OjAg/XRE6j3PdBJVZBzc\n QSwk4+hul9aW0HTXfOWDtJT0qd+MfMt+sKJ6ZSMu+YaYu1cXztJAE7EGNiX4CSnX085F62dGJyu\n /4Z5cgneQZBu1dUOLqle2NQ6Ck0gE+UI0KFY3hwl/2IN50jo95nNyfxgmqwajExu2YDV5ShIcMt\n W0HVNHTytCeYiQqkNFNgZGQN2LKLr1tqdIMeJjA6ZDkXYn3nFIk6Tqo9brFZqBiP1jRVYI/nufM\n 0OoauBnQZZPuRWF85rLEzoECq/RIG/GKf5uhj2JR9ZBQqega0kJsNxV7MtZP1Rd/HQm8/tubxnd\n N0iE=", "X-Developer-Key": "i=dlechner@baylibre.com; a=openpgp;\n fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03", "X-Mailman-Approved-At": "Mon, 09 Feb 2026 19:39:13 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Chris-QJ Chen <chris-qj.chen@mediatek.com>\n\nAdd a basic .dtsi file for MediaTek MT8189. This will suffice until an\nupstream devicetree is available from Linux.\n\nSigned-off-by: Chris-QJ Chen <chris-qj.chen@mediatek.com>\nSigned-off-by: David Lechner <dlechner@baylibre.com>\n---\n arch/arm/dts/mt8189.dtsi | 243 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 243 insertions(+)", "diff": "diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi\nnew file mode 100644\nindex 00000000000..cbece7b89c7\n--- /dev/null\n+++ b/arch/arm/dts/mt8189.dtsi\n@@ -0,0 +1,243 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+/*\n+ * Copyright (C) 2026 MediaTek Inc.\n+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>\n+ */\n+\n+#include <dt-bindings/clock/mediatek,mt8189-clk.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/ {\n+\tcompatible = \"mediatek,mt8189\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tclk26m: oscillator {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <26000000>;\n+\t\tclock-output-names = \"clk26m\";\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x000>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu1: cpu@100 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x100>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu2: cpu@200 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x200>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu3: cpu@300 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x300>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu4: cpu@400 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x400>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu5: cpu@500 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a55\";\n+\t\t\treg = <0x500>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <282>;\n+\t\t};\n+\n+\t\tcpu6: cpu@600 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a78\";\n+\t\t\treg = <0x600>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <1024>;\n+\t\t};\n+\n+\t\tcpu7: cpu@700 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a78\";\n+\t\t\treg = <0x700>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tcapacity-dmips-mhz = <1024>;\n+\t\t};\n+\n+\t\tcpu-map {\n+\t\t\tcluster0 {\n+\t\t\t\tcore0 {\n+\t\t\t\t\tcpu = <&cpu0>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore1 {\n+\t\t\t\t\tcpu = <&cpu1>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore2 {\n+\t\t\t\t\tcpu = <&cpu2>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore3 {\n+\t\t\t\t\tcpu = <&cpu3>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore4 {\n+\t\t\t\t\tcpu = <&cpu4>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore5 {\n+\t\t\t\t\tcpu = <&cpu5>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore6 {\n+\t\t\t\t\tcpu = <&cpu6>;\n+\t\t\t\t};\n+\n+\t\t\t\tcore7 {\n+\t\t\t\t\tcpu = <&cpu7>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tmemory: memory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* This memory size is filled in by the bootloader */\n+\t\treg = <0 0x40000000 0 0>;\n+\t};\n+\n+\tsoc {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tcompatible = \"simple-bus\";\n+\t\tranges;\n+\n+\t\twatchdog: watchdog@1c00a000 {\n+\t\t\tcompatible = \"mediatek,mt8391-wdt\",\n+\t\t\t\t \"mediatek,wdt\";\n+\t\t\treg = <0 0x1c00a000 0 0x100>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tgic: interrupt-controller@c000000 {\n+\t\t\tcompatible = \"arm,gic-v3\";\n+\t\t\treg = <0 0xc000000 0 0x40000>, /* distributor */\n+\t\t\t <0 0xc040000 0 0x200000>; /* redistributor */\n+\t\t\tinterrupt-parent = <&gic>;\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <4>;\n+\t\t\t#redistributor-regions = <1>;\n+\n+\t\t\tppi-partitions {\n+\t\t\t\tppi_cluster0: interrupt-partition-0 {\n+\t\t\t\t\taffinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;\n+\t\t\t\t};\n+\n+\t\t\t\tppi_cluster1: interrupt-partition-1 {\n+\t\t\t\t\taffinity = <&cpu6 &cpu7>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tuart0: serial@11001000 {\n+\t\t\tcompatible = \"mediatek,mt8189-uart\", \"mediatek,mt6577-uart\";\n+\t\t\treg = <0 0x11001000 0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tclocks = <&clk26m>, <&pericfg_ao_clk CLK_PERAO_UART0>;\n+\t\t\tclock-names = \"baud\", \"bus\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmmc0: mmc@11230000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mmc\";\n+\t\t\treg = <0 0x11230000 0 0x10000>,\n+\t\t\t <0 0x11e70000 0 0x1000>;\n+\t\t\tclocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0_H>,\n+\t\t\t\t <&pericfg_ao_clk CLK_PERAO_MSDC0>;\n+\t\t\tclock-names = \"source\", \"hclk\", \"source_cg\";\n+\t\t\tinterrupts = <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tclock-controller@1000c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-apmixedsys\", \"syscon\";\n+\t\t\treg = <0 0x1000c000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tclock-controller@14000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-dispsys\", \"syscon\";\n+\t\t\treg = <0 0x14000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tclock-controller@1e980000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce-d\", \"syscon\";\n+\t\t\treg = <0 0x1e980000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tclock-controller@1e990000 {\n+\t\t\tcompatible = \"mediatek,mt8189-gce-m\", \"syscon\";\n+\t\t\treg = <0 0x1e990000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tclock-controller@1e800000 {\n+\t\t\tcompatible = \"mediatek,mt8189-mm-infra\", \"syscon\";\n+\t\t\treg = <0 0x1e800000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tpericfg_ao_clk: clock-controller@11036000 {\n+\t\t\tcompatible = \"mediatek,mt8189-peri-ao\", \"syscon\";\n+\t\t\treg = <0 0x11036000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\ttopckgen_clk: clock-controller@10000000 {\n+\t\t\tcompatible = \"mediatek,mt8189-topckgen\", \"syscon\";\n+\t\t\treg = <0 0x10000000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tclock-controller@1c00c000 {\n+\t\t\tcompatible = \"mediatek,mt8189-vlpcfg-ao\", \"syscon\";\n+\t\t\treg = <0 0x1c00c000 0 0x1000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "2/4" ] }