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GET /api/patches/2194515/?format=api
{ "id": 2194515, "url": "http://patchwork.ozlabs.org/api/patches/2194515/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260209082454.2097628-10-sherry.sun@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260209082454.2097628-10-sherry.sun@nxp.com>", "list_archive_url": null, "date": "2026-02-09T08:24:52", "name": "[V4,09/11] arm64: dts: imx8mq: Add Root Port node and PERST property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4aeb9be7c34c8657dbafaf1b8c4af7321a90c570", "submitter": { "id": 77063, "url": "http://patchwork.ozlabs.org/api/people/77063/?format=api", "name": "Sherry Sun", "email": "sherry.sun@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260209082454.2097628-10-sherry.sun@nxp.com/mbox/", "series": [ { "id": 491476, "url": "http://patchwork.ozlabs.org/api/series/491476/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491476", "date": "2026-02-09T08:24:43", "name": "pci-imx6: Add support for parsing the reset property in new Root Port binding", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/491476/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194515/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194515/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-46995-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=q7w42lO/mWxDp/BZV+doM4rBKxlvzdjyqDCu633S3Ng=;\n b=mj8lsyBb/T9zmor6f0XPlc5DboO4lK2XsHrc3KHieMicOcmQHmXgP98TyMjOEhJ9Nljq6ueNlyzdyYGW7TPYjOYKcL/oyVJH0SZbu4iFyliNWr4JVTblaIAo17EN+emY3YxFJXpsdegu8xqDERnl7wx30PauwzpUXFGBDAhwPwBAVW7aThYRuF+0e39vmyMpaGlma6maie7RLo60RQpctzJu1MYBW2Mrf73xOe2CnNBshUhs+xM94ClXOYhu7XEpnl3TrLT52oSOG6SdvQlb9rV9XhhBZACzhdELd6nIptQ68rNIWlyyzzV/cqONuA0YrmKoW65EEiynzlWVuE4FDA==", "From": "Sherry Sun <sherry.sun@nxp.com>", "To": "hongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de,\n\tFrank.Li@nxp.com,\n\tbhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\ts.hauer@pengutronix.de,\n\tfestevam@gmail.com,\n\twill@kernel.org", "Cc": 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"X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c869250f-e2d8-42a1-4d68-08de67b4aeb3", "X-MS-Exchange-CrossTenant-AuthSource": "VI0PR04MB12114.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Feb 2026 08:24:45.8940\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n RM9DmHyOINUXiNMZ/1i0DaApT7tn1BoLaICR9j2cfnNm2BF4pvmsGib990ltvEbI2G9S5rXhf8gwwavqgOQnlA==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB8PR04MB7180" }, "content": "Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun <sherry.sun@nxp.com>\n---\n arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 +++++++++\n arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++++++++++++++++++\n 2 files changed, 32 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts\nindex d48f901487d4..e7d87ea81b69 100644\n--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts\n@@ -369,6 +369,7 @@ mipi_dsi_out: endpoint {\n &pcie0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pcie0>;\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;\n \tclocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,\n \t\t <&pcie0_refclk>,\n@@ -389,9 +390,14 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcie0_port0 {\n+\treset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcie1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pcie1>;\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;\n \tclocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,\n \t\t <&pcie0_refclk>,\n@@ -414,6 +420,10 @@ &pcie1_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcie1_port0 {\n+\treset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;\n+};\n+\n &pgc_gpu {\n \tpower-supply = <&sw1a_reg>;\n };\ndiff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi\nindex 607962f807be..de2ba4ee9da6 100644\n--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi\n@@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 {\n \t\t\tassigned-clock-rates = <250000000>, <100000000>,\n \t\t\t <10000000>;\n \t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie0_port0: pcie@0 {\n+\t\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\t\tdevice_type = \"pci\";\n+\t\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t\tranges;\n+\t\t\t};\n \t\t};\n \n \t\tpcie0_ep: pcie-ep@33800000 {\n@@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 {\n \t\t\tassigned-clock-rates = <250000000>, <100000000>,\n \t\t\t <10000000>;\n \t\t\tstatus = \"disabled\";\n+\n+\t\t\tpcie1_port0: pcie@0 {\n+\t\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\t\tdevice_type = \"pci\";\n+\t\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t\tranges;\n+\t\t\t};\n \t\t};\n \n \t\tpcie1_ep: pcie-ep@33c00000 {\n", "prefixes": [ "V4", "09/11" ] }