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GET /api/patches/2194507/?format=api
{ "id": 2194507, "url": "http://patchwork.ozlabs.org/api/patches/2194507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260209082454.2097628-4-sherry.sun@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260209082454.2097628-4-sherry.sun@nxp.com>", "list_archive_url": null, "date": "2026-02-09T08:24:46", "name": "[V4,03/11] PCI: imx6: Add support for parsing the reset property in new Root Port binding", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3e1be39de5d84e5e3737b0613a39c2126b13e17c", "submitter": { "id": 77063, "url": "http://patchwork.ozlabs.org/api/people/77063/?format=api", "name": "Sherry Sun", "email": "sherry.sun@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260209082454.2097628-4-sherry.sun@nxp.com/mbox/", "series": [ { "id": 491476, "url": "http://patchwork.ozlabs.org/api/series/491476/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491476", "date": "2026-02-09T08:24:43", "name": "pci-imx6: Add support for parsing the reset property in new Root Port binding", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/491476/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194507/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194507/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-46989-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=2s6odGd2U/n4yPr1xH6VkYL/JCZkvSYjaJv+MnG0Tm8=;\n b=UZY9wGbBCN87GtEvfILWGJFm+xXgsSmkFGUp8AmRtjtOWY6msr7zXNAY5Yk0GLCJrLFSOw7BuPRCZVmlYwH8SItVNoVWZjHqKXzYme7YCAPAt/M9zB3ot0RgFekepENcgdTe0IJavKobPo/02OzvI98b5KKieA0NrRbqe4+1pRxwjePiIcnl7s0APLGrRFNG3kNFIQhGPOp/FT8ZeZprhFC73MTE+bBEsKgOk7xvP2hfi/KzkVP3hEVN1cecSz8jO10giYfDZYgh65WgQ8Wk28lhXEAnLziff8WcPFtOiEyUfLsip/98eO01Kl0uk7Wi7F7e/kO4BcOh63FhCGYgrQ==", "From": "Sherry Sun <sherry.sun@nxp.com>", "To": "hongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de,\n\tFrank.Li@nxp.com,\n\tbhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\ts.hauer@pengutronix.de,\n\tfestevam@gmail.com,\n\twill@kernel.org", "Cc": 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"X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 03924f87-addb-4815-0e13-08de67b497b9", "X-MS-Exchange-CrossTenant-AuthSource": "VI0PR04MB12114.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Feb 2026 08:24:07.1953\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n oVPDzNkfQdHLmuRU3B0lU8zTjsAYpiP4J9Km7JbKsxgRHgBychxpG4+5J9V39kznkb97CeJ6ynb/e5ZF8TqICg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "GV2PR04MB11834" }, "content": "DT binding allows specifying 'reset' property in both host bridge and\nRoot Port nodes, but specifying in the host bridge node is marked as\ndeprecated. So add support for parsing the new binding that uses\n'reset-gpios' property for PERST#.\n\nThe initial idea is to add the PCIe M.2 KeyE connector support and PCI\npower control framework to the pcie-imx6 driver. Since the new\nM.2/pwrctrl model is implemented based on Root Ports and requires the\npwrctrl driver to bind to a Root Port device, we need to introduce a\nRoot Port child node on i.MX boards that provide an M.2 connector.\n\nTo follow a more standardized DT structure, it also makes sense to move\nthe reset-gpios and wake-gpios properties into the Root Port node. These\nsignals logically belong to the Root Port rather than the host bridge,\nand placing them there aligns with the new M.2/pwrctrl model.\n\nTo maintain DT backwards compatibility, fallback to the legacy method of\nparsing the host bridge node if the reset property is not present in the\nRoot Port node.\n\nSigned-off-by: Sherry Sun <sherry.sun@nxp.com>\n---\n drivers/pci/controller/dwc/pci-imx6.c | 69 +++++++++++++++++++++------\n 1 file changed, 55 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex a5b8d0b71677..317a969da96b 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -34,6 +34,7 @@\n #include <linux/pm_runtime.h>\n \n #include \"../../pci.h\"\n+#include \"../pci-host-common.h\"\n #include \"pcie-designware.h\"\n \n #define IMX8MQ_GPR_PCIE_REF_USE_PAD\t\tBIT(9)\n@@ -150,8 +151,8 @@ struct imx_lut_data {\n \n struct imx_pcie {\n \tstruct dw_pcie\t\t*pci;\n-\tstruct gpio_desc\t*reset_gpiod;\n \tstruct clk_bulk_data\t*clks;\n+\tstruct list_head\tports;\n \tint\t\t\tnum_clks;\n \tbool\t\t\tsupports_clkreq;\n \tbool\t\t\tenable_ext_refclk;\n@@ -897,29 +898,34 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)\n \n static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)\n {\n+\tstruct pci_host_port *port;\n+\n \treset_control_assert(imx_pcie->pciephy_reset);\n \n \tif (imx_pcie->drvdata->core_reset)\n \t\timx_pcie->drvdata->core_reset(imx_pcie, true);\n \n \t/* Some boards don't have PCIe reset GPIO. */\n-\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1);\n+\tlist_for_each_entry(port, &imx_pcie->ports, list)\n+\t\tgpiod_set_value_cansleep(port->reset, 1);\n }\n \n static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)\n {\n+\tstruct pci_host_port *port;\n+\n \treset_control_deassert(imx_pcie->pciephy_reset);\n \n \tif (imx_pcie->drvdata->core_reset)\n \t\timx_pcie->drvdata->core_reset(imx_pcie, false);\n \n \t/* Some boards don't have PCIe reset GPIO. */\n-\tif (imx_pcie->reset_gpiod) {\n-\t\tmsleep(100);\n-\t\tgpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0);\n-\t\t/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */\n-\t\tmsleep(100);\n-\t}\n+\tlist_for_each_entry(port, &imx_pcie->ports, list)\n+\t\tif (port->reset) {\n+\t\t\tmsleep(PCIE_T_PVPERL_MS);\n+\t\t\tgpiod_set_value_cansleep(port->reset, 0);\n+\t\t\tmsleep(PCIE_RESET_CONFIG_WAIT_MS);\n+\t\t}\n \n \treturn 0;\n }\n@@ -1642,6 +1648,27 @@ static const struct dev_pm_ops imx_pcie_pm_ops = {\n \t\t\t\t imx_pcie_resume_noirq)\n };\n \n+static int imx_pcie_parse_legacy_binding(struct imx_pcie *pcie)\n+{\n+\tstruct device *dev = pcie->pci->dev;\n+\tstruct pci_host_port *port;\n+\tstruct gpio_desc *reset;\n+\n+\treset = devm_gpiod_get_optional(dev, \"reset\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(reset))\n+\t\treturn PTR_ERR(reset);\n+\n+\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n+\tif (!port)\n+\t\treturn -ENOMEM;\n+\n+\tport->reset = reset;\n+\tINIT_LIST_HEAD(&port->list);\n+\tlist_add_tail(&port->list, &pcie->ports);\n+\n+\treturn 0;\n+}\n+\n static int imx_pcie_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -1660,6 +1687,8 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \tif (!pci)\n \t\treturn -ENOMEM;\n \n+\tINIT_LIST_HEAD(&imx_pcie->ports);\n+\n \tpci->dev = dev;\n \tpci->ops = &dw_pcie_ops;\n \n@@ -1688,12 +1717,24 @@ static int imx_pcie_probe(struct platform_device *pdev)\n \t\t\treturn PTR_ERR(imx_pcie->phy_base);\n \t}\n \n-\t/* Fetch GPIOs */\n-\timx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, \"reset\", GPIOD_OUT_HIGH);\n-\tif (IS_ERR(imx_pcie->reset_gpiod))\n-\t\treturn dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod),\n-\t\t\t\t \"unable to get reset gpio\\n\");\n-\tgpiod_set_consumer_name(imx_pcie->reset_gpiod, \"PCIe reset\");\n+\tret = pci_host_common_parse_ports(dev, &imx_pcie->ports);\n+\tif (ret) {\n+\t\tif (ret != -ENOENT)\n+\t\t\treturn dev_err_probe(dev, ret, \"Failed to parse Root Port: %d\\n\", ret);\n+\n+\t\t/*\n+\t\t * In the case of properties not populated in Root Port node,\n+\t\t * fallback to the legacy method of parsing the Host Bridge\n+\t\t * node. This is to maintain DT backwards compatibility.\n+\t\t */\n+\t\tret = imx_pcie_parse_legacy_binding(imx_pcie);\n+\t\tif (ret)\n+\t\t\treturn dev_err_probe(dev, ret, \"Unable to get reset gpio: %d\\n\", ret);\n+\t}\n+\n+\tret = devm_add_action_or_reset(dev, pci_host_common_delete_ports, &imx_pcie->ports);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Fetch clocks */\n \timx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks);\n", "prefixes": [ "V4", "03/11" ] }