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{ "id": 2194482, "url": "http://patchwork.ozlabs.org/api/patches/2194482/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260209065428.2528191-1-jie.mei@oss.cipunited.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260209065428.2528191-1-jie.mei@oss.cipunited.com>", "list_archive_url": null, "date": "2026-02-09T06:54:28", "name": "MIPS: Add BITSWAP/DBITSWAP instruction for MIPSr6", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8657c6b82990d95fd723a1e9cc70ebb462ef56ad", "submitter": { "id": 86381, "url": "http://patchwork.ozlabs.org/api/people/86381/?format=api", "name": "Jie Mei", "email": "jie.mei@oss.cipunited.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260209065428.2528191-1-jie.mei@oss.cipunited.com/mbox/", "series": [ { "id": 491468, "url": "http://patchwork.ozlabs.org/api/series/491468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491468", "date": "2026-02-09T06:54:28", "name": "MIPS: Add BITSWAP/DBITSWAP instruction for MIPSr6", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194482/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194482/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com\n header.a=rsa-sha256 header.s=feishu2303200042 header.b=gmmekkAq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n s=feishu2303200042; d=oss.cipunited.com; t=1770620094;\n h=from:subject:mime-version:from:date:message-id:subject:to:cc:\n reply-to:content-type:mime-version:in-reply-to:message-id;\n bh=6mBuQ0fq89ZgSmJ9DV1boy1tFeyFYxu2DC0Rw10g4n0=;\n b=gmmekkAq0DpbJIZCZFsBVplt8xC3+aJK/GGLGN4+K+GC06XFVQn1I1NEfP3QwqpMxMz0LF\n xfajmq/TkFpZJz4u8qgRupINPy2Sjzxnw5e1JTSGjdU7uA9ubAkqpqFc1lv5HMeFnmYKnc\n oSOBiVvv/+cSxVFcguoEsi+mv9cVOg/SOmbM4q2Nb2azWcqx9TKTYT26Ms/9Hi39Uct2uc\n hJGFKOwqp1vuIkWJXubbMqBpYQZFk9/u10ZwoBZeytkVz48ydYxOcoXE1Dy7PORlx0ngNY\n RHxoi8TAUK5gTQ//GH06oj+3XNYT1s/jQbt/DM0P0OgQerhyVruP70Mv3yEkxg==", "X-Original-From": "Jie Mei <jie.mei@oss.cipunited.com>", "X-Mailer": "git-send-email 2.52.0", "Content-Type": "text/plain; charset=UTF-8", "Mime-Version": "1.0", "Content-Transfer-Encoding": "quoted-printable", "Subject": "[PATCH] MIPS: Add BITSWAP/DBITSWAP instruction for MIPSr6", "Message-Id": "<20260209065428.2528191-1-jie.mei@oss.cipunited.com>", "X-Lms-Return-Path": "\n <lba+2698984bc+26a2d7+gcc.gnu.org+jie.mei@oss.cipunited.com>", "Cc": "\"YunQiang Su\" <syq@gcc.gnu.org>, \"Rongrong\" <rongrong@oss.cipunited.com>", "From": "\"Jie Mei\" <jie.mei@oss.cipunited.com>", "To": "<gcc-patches@gcc.gnu.org>", "Date": "Mon, 9 Feb 2026 14:54:28 +0800", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "BITSWAP is a byte-wise bitreverse in MIPSr6. For example,\nBITSWAP(0x44332211) => 0x22cc4488.\nDBITSWAP is similar to BITSWAP but for 64 bit.\n\nThis patch adds BITSWAP/DBITSWAP instrutions with corresponding tests.\n\ngcc/ChangeLog:\n\n\t* config/mips/i6400.md (i6400_int_arith): Include bitswap\n\ttype.\n\t* config/mips/mips-ftypes.def: Add function types for\n\tDBITSWAP builtins.\n\t* config/mips/mips.cc (CODE_FOR_mipsr6_bitswap)\n\t(CODE_FOR_mipsr6_dbitswap): New code_aliasing macros.\n\t(mips_builtins): Add mips32r6 bitswap, dbitswap builtins.\n\t* config/mips/mips.h (ISA_HAS_BITSWAP): Define a new macro.\n\t(ISA_HAS_DBITSWAP): Same as above.\n\t* config/mips/mips.md (UNSPEC_BITSWAP): New unspec.\n\t(type): Add bitswap.\n\t(<GPR:d>bitswap): Generates BITSWAP/DBITSWAP instructions.\n\t* config/mips/p6600.md (p6600_int_arith_4): Include bitswap\n\ttype.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/mips/bitswap.c: New test for MIPSr6.\n\t* gcc.target/mips/dbitswap.c: Same as above.\n\nCo-developed-by: Rong Zhang <rongrong@oss.cipunited.com>\nSigned-off-by: Rong Zhang <rongrong@oss.cipunited.com>\nSigned-off-by: Jie Mei <jie.mei@oss.cipunited.com>\n---\n gcc/config/mips/i6400.md | 4 +-\n gcc/config/mips/mips-ftypes.def | 1 +\n gcc/config/mips/mips.cc | 4 +\n gcc/config/mips/mips.h | 6 +\n gcc/config/mips/mips.md | 20 +++-\n gcc/config/mips/p6600.md | 4 +-\n gcc/testsuite/gcc.target/mips/bitswap.c | 141 +++++++++++++++++++++++\n gcc/testsuite/gcc.target/mips/dbitswap.c | 129 +++++++++++++++++++++\n 8 files changed, 302 insertions(+), 7 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/mips/bitswap.c\n create mode 100644 gcc/testsuite/gcc.target/mips/dbitswap.c", "diff": "diff --git a/gcc/config/mips/i6400.md b/gcc/config/mips/i6400.md\nindex 62f70c1e816..8eb377a959d 100644\n--- a/gcc/config/mips/i6400.md\n+++ b/gcc/config/mips/i6400.md\n@@ -296,10 +296,10 @@\n (eq_attr \"alu_type\" \"add,sub,or,xor,nor\"))\n \"i6400_control_alu0 | i6400_agen_alu1\")\n \n-;; shifts, clo, clz, cond move, arith\n+;; shifts, clo, clz, cond move, arith, bitswap\n (define_insn_reservation \"i6400_int_arith\" 1\n (and (eq_attr \"cpu\" \"i6400\")\n- (eq_attr \"type\" \"shift,slt,move,clz,condmove,arith\"))\n+ (eq_attr \"type\" \"shift,slt,move,clz,condmove,arith,bitswap\"))\n \"i6400_control_alu0 | i6400_agen_alu1\")\n \n ;; nop\ndiff --git a/gcc/config/mips/mips-ftypes.def b/gcc/config/mips/mips-ftypes.def\nindex fb72661c682..70fd61e2af5 100644\n--- a/gcc/config/mips/mips-ftypes.def\n+++ b/gcc/config/mips/mips-ftypes.def\n@@ -37,6 +37,7 @@ DEF_MIPS_FTYPE (1, (DF, DF))\n DEF_MIPS_FTYPE (2, (DF, DF, DF))\n DEF_MIPS_FTYPE (1, (DF, V2DF))\n \n+DEF_MIPS_FTYPE (1, (DI, DI))\n DEF_MIPS_FTYPE (2, (DI, DI, DI))\n DEF_MIPS_FTYPE (2, (DI, DI, SI))\n DEF_MIPS_FTYPE (3, (DI, DI, SI, SI))\ndiff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc\nindex cc45a195b89..b8fc6b3cb0c 100644\n--- a/gcc/config/mips/mips.cc\n+++ b/gcc/config/mips/mips.cc\n@@ -16214,6 +16214,8 @@ AVAIL_NON_MIPS16 (r6, mips_isa_rev >= 6)\n #define CODE_FOR_mipsr6_max_a_d CODE_FOR_fmax_a_df\n #define CODE_FOR_mipsr6_class_s CODE_FOR_fclass_sf\n #define CODE_FOR_mipsr6_class_d CODE_FOR_fclass_df\n+#define CODE_FOR_mipsr6_bitswap CODE_FOR_bitswap\n+#define CODE_FOR_mipsr6_dbitswap CODE_FOR_dbitswap\n \n static const struct mips_builtin_description mips_builtins[] = {\n #define MIPS_GET_FCSR 0\n@@ -17044,6 +17046,8 @@ static const struct mips_builtin_description mips_builtins[] = {\n MIPSR6_BUILTIN_PURE (max_a_d, MIPS_DF_FTYPE_DF_DF),\n MIPSR6_BUILTIN_PURE (class_s, MIPS_SF_FTYPE_SF),\n MIPSR6_BUILTIN_PURE (class_d, MIPS_DF_FTYPE_DF),\n+ MIPSR6_BUILTIN_PURE (bitswap, MIPS_SI_FTYPE_SI),\n+ MIPSR6_BUILTIN_PURE (dbitswap, MIPS_DI_FTYPE_DI),\n };\n \n /* Index I is the function declaration for mips_builtins[I], or null if the\ndiff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h\nindex f52d0d2358c..8a930b52942 100644\n--- a/gcc/config/mips/mips.h\n+++ b/gcc/config/mips/mips.h\n@@ -1267,6 +1267,12 @@ struct mips_cpu_info {\n /* Similar to WSBH but for 32 bit words (byte swap within a word). */\n #define ISA_HAS_WSBW\t\t(TARGET_ALLEGREX)\n \n+/* ISA has the BITSWAP (swaps bits in each byte) instruction. */\n+#define ISA_HAS_BITSWAP\t\t(mips_isa_rev >= 6)\n+\n+/* Similar to BITSWAP but for 64 bit (swaps bits in each byte). */\n+#define ISA_HAS_DBITSWAP\t(TARGET_64BIT && mips_isa_rev >= 6)\n+\n /* ISA has data prefetch instructions. This controls use of 'pref'. */\n #define ISA_HAS_PREFETCH\t((ISA_MIPS4\t\t\t\t\\\n \t\t\t\t || TARGET_LOONGSON_2EF\t\t\\\ndiff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md\nindex 85e7d67901f..24369163f44 100644\n--- a/gcc/config/mips/mips.md\n+++ b/gcc/config/mips/mips.md\n@@ -86,6 +86,7 @@\n UNSPEC_WSBH\n UNSPEC_DSBH\n UNSPEC_DSHD\n+ UNSPEC_BITSWAP\n \n ;; Floating-point moves.\n UNSPEC_LOAD_LOW\n@@ -396,9 +397,9 @@\n \"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,\n prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,\n shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,\n- fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,\n- frsqrt,frsqrt1,frsqrt2,fminmax,frint,fclass,dspmac,dspmacsat,accext,\n- accmod,dspalu,dspalusat,multi,atomic,syncloop,nop,ghost,multimem,\n+ bitswap,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,\n+ fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,fminmax,frint,fclass,dspmac,dspmacsat,\n+ accext,accmod,dspalu,dspalusat,multi,atomic,syncloop,nop,ghost,multimem,\n simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,\n simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,\n simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,\n@@ -6102,6 +6103,19 @@\n \"TARGET_64BIT && ISA_HAS_WSBH\"\n \"dshd\\t%0,%1\"\n [(set_attr \"type\" \"shift\")])\n+\n+;;\n+;; Swaps (reverses) bits in each byte\n+;;\n+\n+(define_insn \"<GPR:d>bitswap\"\n+ [(set (match_operand:GPR 0 \"register_operand\" \"=d\")\n+\t(unspec:GPR [(use (match_operand:GPR 1 \"register_operand\" \"d\"))]\n+\t\t UNSPEC_BITSWAP))]\n+ \"ISA_HAS_<GPR:D>BITSWAP\"\n+ \"<GPR:d>bitswap\\t%0,%1\"\n+ [(set_attr \"type\" \"bitswap\")\n+ (set_attr \"mode\" \"<GPR:MODE>\")])\n \f\n ;;\n ;; ....................\ndiff --git a/gcc/config/mips/p6600.md b/gcc/config/mips/p6600.md\nindex 05c426e8134..bb6bb128d61 100644\n--- a/gcc/config/mips/p6600.md\n+++ b/gcc/config/mips/p6600.md\n@@ -269,10 +269,10 @@\n (eq_attr \"alu_type\" \"and,not,nor,sub\"))\n \"p6600_alq_alu\")\n \n-;; srl, sra, rotr, slt, sllv, srlv\n+;; srl, sra, rotr, slt, sllv, srlv, bitswap\n (define_insn_reservation \"p6600_int_arith_4\" 1\n (and (eq_attr \"cpu\" \"p6600\")\n- (eq_attr \"type\" \"shift,slt,move\"))\n+ (eq_attr \"type\" \"shift,slt,move,bitswap\"))\n \"p6600_alq_alu | p6600_agq_al2\")\n \n ;; nop\ndiff --git a/gcc/testsuite/gcc.target/mips/bitswap.c b/gcc/testsuite/gcc.target/mips/bitswap.c\nnew file mode 100644\nindex 00000000000..495c863a40e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/mips/bitswap.c\n@@ -0,0 +1,141 @@\n+/* { dg-do compile } */\n+/* { dg-options \"isa_rev>=6 -mabi=32 (REQUIRES_STDLIB)\" } */\n+/* { dg-final { scan-assembler-times \"\\tbitswap\\t\" 22 } } */\n+/* { dg-final { scan-assembler-times \"\\tseb\\t\" 4 } } */\n+/* { dg-final { scan-assembler-times \"\\tseh\\t\" 6 } } */\n+/* { dg-skip-if \"code quality test\" { *-*-* } { \"-O0\" } { \"\" } } */\n+/* Skip -O0 so that we can test against SEB and SEH. */\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <stdint.h>\n+\n+NOMIPS16 int main()\n+{\n+\n+ int8_t i8_a, i8_b, i8_x;\t\n+ int16_t i16_a, i16_b, i16_x;\n+ int32_t i32_a, i32_b, i32_x;\n+\n+ i8_a = 0x01;\n+ i8_b = 0x80;\n+ i8_x = __builtin_mipsr6_bitswap (i8_a);\n+ if (i8_x != i8_b)\n+ abort ();\n+\n+ i8_a = 0x10;\n+ i8_b = 0x08;\n+ i8_x = __builtin_mipsr6_bitswap (i8_a);\n+ if (i8_x != i8_b)\n+ abort ();\n+\n+ i8_a = 0x23;\n+ i8_b = 0xc4;\n+ i8_x = __builtin_mipsr6_bitswap (i8_a);\n+ if (i8_x != i8_b)\n+ abort ();\n+ i8_x = __builtin_mipsr6_bitswap (i8_b);\n+ if (i8_x != i8_a)\n+ abort ();\n+\n+ i16_a = 0x0002;\n+ i16_b = 0x0040;\n+ i16_x = __builtin_mipsr6_bitswap (i16_a);\n+ if (i16_x != i16_b)\n+ abort ();\n+\n+ i16_a = 0x0020;\n+ i16_b = 0x0004;\n+ i16_x = __builtin_mipsr6_bitswap (i16_a);\n+ if (i16_x != i16_b)\n+ abort ();\n+\n+ i16_a = 0x0200;\n+ i16_b = 0x4000;\n+ i16_x = __builtin_mipsr6_bitswap (i16_a);\n+ if (i16_x != i16_b)\n+ abort ();\n+\n+ i16_a = 0x2000;\n+ i16_b = 0x0400;\n+ i16_x = __builtin_mipsr6_bitswap (i16_a);\n+ if (i16_x != i16_b)\n+ abort ();\n+\n+ i16_a = 0x1234;\n+ i16_b = 0x482c;\n+ i16_x = __builtin_mipsr6_bitswap (i16_a);\n+ if (i16_x != i16_b)\n+ abort ();\n+ i16_x = __builtin_mipsr6_bitswap (i16_b);\n+ if (i16_x != i16_a)\n+ abort ();\n+\n+ i32_a = 0x00000003;\n+ i32_b = 0x000000c0;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x00000030;\n+ i32_b = 0x0000000c;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x00000300;\n+ i32_b = 0x0000c000;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x00003000;\n+ i32_b = 0x00000c00;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x00030000;\n+ i32_b = 0x00c00000;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x00300000;\n+ i32_b = 0x000c0000;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x03000000;\n+ i32_b = 0xc0000000;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x30000000;\n+ i32_b = 0x0c000000;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+\n+ i32_a = 0x11223344;\n+ i32_b = 0x8844cc22;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+ i32_x = __builtin_mipsr6_bitswap (i32_b);\n+ if (i32_x != i32_a)\n+ abort ();\n+\n+ i32_a = 0x3baf6dec;\n+ i32_b = 0xdcf5b637;\n+ i32_x = __builtin_mipsr6_bitswap (i32_a);\n+ if (i32_x != i32_b)\n+ abort ();\n+ i32_x = __builtin_mipsr6_bitswap (i32_b);\n+ if (i32_x != i32_a)\n+ abort ();\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/gcc.target/mips/dbitswap.c b/gcc/testsuite/gcc.target/mips/dbitswap.c\nnew file mode 100644\nindex 00000000000..be4804abf10\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/mips/dbitswap.c\n@@ -0,0 +1,129 @@\n+/* { dg-do compile } */\n+/* { dg-options \"isa_rev>=6 -mabi=64 (REQUIRES_STDLIB)\" } */\n+/* { dg-final { scan-assembler-times \"\\tdbitswap\\t\" 20 } } */\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <stdint.h>\n+\n+NOMIPS16 int main()\n+{\n+\n+ int64_t i64_a, i64_b, i64_x;\n+\n+ i64_a = 0x0000000000000001LL;\n+ i64_b = 0x0000000000000080LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000000000010LL;\n+ i64_b = 0x0000000000000008LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000000000100LL;\n+ i64_b = 0x0000000000008000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000000001000LL;\n+ i64_b = 0x0000000000000800LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000000010000LL;\n+ i64_b = 0x0000000000800000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000000100000LL;\n+ i64_b = 0x0000000000080000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000001000000LL;\n+ i64_b = 0x0000000080000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000010000000LL;\n+ i64_b = 0x0000000008000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000000100000000LL;\n+ i64_b = 0x0000008000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000001000000000LL;\n+ i64_b = 0x0000000800000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000010000000000LL;\n+ i64_b = 0x0000800000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0000100000000000LL;\n+ i64_b = 0x0000080000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0001000000000000LL;\n+ i64_b = 0x0080000000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0010000000000000LL;\n+ i64_b = 0x0008000000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x0100000000000000LL;\n+ i64_b = 0x8000000000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x1000000000000000LL;\n+ i64_b = 0x0800000000000000LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+\n+ i64_a = 0x1122334455667788LL;\n+ i64_b = 0x8844cc22aa66ee11LL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+ i64_x = __builtin_mipsr6_dbitswap (i64_b);\n+ if (i64_x != i64_a)\n+ abort ();\n+\n+ i64_a = 0x71e9a43a6791033dLL;\n+ i64_b = 0x8e97255ce689c0bcLL;\n+ i64_x = __builtin_mipsr6_dbitswap (i64_a);\n+ if (i64_x != i64_b)\n+ abort ();\n+ i64_x = __builtin_mipsr6_dbitswap (i64_b);\n+ if (i64_x != i64_a)\n+ abort ();\n+\n+ return 0;\n+}\n", "prefixes": [] }