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GET /api/patches/2194432/?format=api
{ "id": 2194432, "url": "http://patchwork.ozlabs.org/api/patches/2194432/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/patch/20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-2-a2f59e97a92d@axiado.com/", "project": { "id": 56, "url": "http://patchwork.ozlabs.org/api/projects/56/?format=api", "name": "OpenBMC development", "link_name": "openbmc", "list_id": "openbmc.lists.ozlabs.org", "list_email": "openbmc@lists.ozlabs.org", "web_url": "http://github.com/openbmc/", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-2-a2f59e97a92d@axiado.com>", "list_archive_url": null, "date": "2026-02-06T08:22:09", "name": "[v2,2/4] phy: axiado: add Axiado eMMC PHY driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "57b488bc7d3ab5579fe1bae0003ee5581ba0cb89", "submitter": { "id": 91696, "url": "http://patchwork.ozlabs.org/api/people/91696/?format=api", "name": "Tzu-Hao Wei", "email": "twei@axiado.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openbmc/patch/20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-2-a2f59e97a92d@axiado.com/mbox/", "series": [ { "id": 491445, "url": "http://patchwork.ozlabs.org/api/series/491445/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openbmc/list/?series=491445", "date": "2026-02-06T08:22:11", "name": "Add eMMC PHY support for Axiado AX3000 SoC", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491445/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194432/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194432/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <openbmc+bounces-1337-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "openbmc@lists.ozlabs.org" ], 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"In-Reply-To": "\n <20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-0-a2f59e97a92d@axiado.com>", "To": "SriNavmani A <srinavmani@axiado.com>,\n Prasad Bolisetty <pbolisetty@axiado.com>, Vinod Koul <vkoul@kernel.org>,\n Neil Armstrong <neil.armstrong@linaro.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-phy@lists.infradead.org, devicetree@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n openbmc@lists.ozlabs.org, Tzu-Hao Wei <twei@axiado.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=9234; i=twei@axiado.com;\n h=from:subject:message-id; bh=XTDIF1da24JB5QFFJCOouIbpzH8ph5S2EmF/RAzCbeQ=;\n b=owEB7QES/pANAwAKAXgQMF3EWvHXAcsmYgBphaS5oIwXbgXd6c66r7J12ZIKxpG7oPionERk7\n bzW4XCg6g2JAbMEAAEKAB0WIQSZyWINOowtFmDvdYF4EDBdxFrx1wUCaYWkuQAKCRB4EDBdxFrx\n 1wI+C/9nbebu7Y3iM2AdL1gsMbxDGHt3yAHvEbodabmM637ABzqSfh/3DT+PSPo5aHpid9pXf2F\n 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"X-OriginatorOrg": "axiado.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d3f091a-0e1c-4e33-b8ca-08de6558d866", "X-MS-Exchange-CrossTenant-AuthSource": "PH0PR18MB4558.namprd18.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Feb 2026 08:22:19.6691\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "ff2db17c-4338-408e-9036-2dee8e3e17d7", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 8WPyxyYopPvFDyfPYaSCeiYgQRlvQBnvfCHHLj8MaCgt+8qBd2fj6U1sMqf1Lnc6", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR18MB3667", "X-Spam-Status": "No, score=-0.2 required=5.0 tests=ARC_SIGNED,ARC_VALID,\n\tDKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,\n\tSPF_HELO_PASS,SPF_PASS autolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "From: SriNavmani A <srinavmani@axiado.com>\n\nIt provides the required configurations for Axiado eMMC PHY driver for\nHS200 mode.\n\nSigned-off-by: SriNavmani A <srinavmani@axiado.com>\nCo-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>\nSigned-off-by: Prasad Bolisetty <pbolisetty@axiado.com>\nSigned-off-by: Tzu-Hao Wei <twei@axiado.com>\n---\n drivers/phy/Kconfig | 1 +\n drivers/phy/Makefile | 1 +\n drivers/phy/axiado/Kconfig | 11 ++\n drivers/phy/axiado/Makefile | 1 +\n drivers/phy/axiado/phy-axiado-emmc.c | 221 +++++++++++++++++++++++++++++++++++\n 5 files changed, 235 insertions(+)", "diff": "diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig\nindex 678dd0452f0aa0597773433f04d2a9ba77474d2a..b802274ea45a84bd36d7c0b7fb90e368a5c018b4 100644\n--- a/drivers/phy/Kconfig\n+++ b/drivers/phy/Kconfig\n@@ -103,6 +103,7 @@ config PHY_NXP_PTN3222\n \n source \"drivers/phy/allwinner/Kconfig\"\n source \"drivers/phy/amlogic/Kconfig\"\n+source \"drivers/phy/axiado/Kconfig\"\n source \"drivers/phy/broadcom/Kconfig\"\n source \"drivers/phy/cadence/Kconfig\"\n source \"drivers/phy/freescale/Kconfig\"\ndiff --git a/drivers/phy/Makefile b/drivers/phy/Makefile\nindex bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..f1b9e4a8673bcde3fdc0fdc06a3deddb5785ced1 100644\n--- a/drivers/phy/Makefile\n+++ b/drivers/phy/Makefile\n@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE)\t\t+= phy-airoha-pcie.o\n obj-$(CONFIG_PHY_NXP_PTN3222)\t\t+= phy-nxp-ptn3222.o\n obj-y\t\t\t\t\t+= allwinner/\t\\\n \t\t\t\t\t amlogic/\t\\\n+\t\t\t\t\t axiado/\t\\\n \t\t\t\t\t broadcom/\t\\\n \t\t\t\t\t cadence/\t\\\n \t\t\t\t\t freescale/\t\\\ndiff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..d159e0345345987c7f48dcd12d3237997735d2b5\n--- /dev/null\n+++ b/drivers/phy/axiado/Kconfig\n@@ -0,0 +1,11 @@\n+#\n+# PHY drivers for Axiado platforms\n+#\n+\n+config PHY_AX3000_EMMC\n+\ttristate \"Axiado eMMC PHY driver\"\n+\tdepends on OF && (ARCH_AXIADO || COMPILE_TEST)\n+\tselect GENERIC_PHY\n+\thelp\n+\t Enables this to support for the AX3000 EMMC PHY driver.\n+\t If unsure, say N.\ndiff --git a/drivers/phy/axiado/Makefile b/drivers/phy/axiado/Makefile\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..1e2b1ba016092eaffdbd7acbd9cdc8577d79b35c\n--- /dev/null\n+++ b/drivers/phy/axiado/Makefile\n@@ -0,0 +1 @@\n+obj-$(CONFIG_PHY_AX3000_EMMC)\t\t+= phy-axiado-emmc.o\ndiff --git a/drivers/phy/axiado/phy-axiado-emmc.c b/drivers/phy/axiado/phy-axiado-emmc.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..28d2a30c3b35ee7dba917487959e226941e8ea4b\n--- /dev/null\n+++ b/drivers/phy/axiado/phy-axiado-emmc.c\n@@ -0,0 +1,221 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Axiado eMMC PHY driver\n+ *\n+ * Copyright (C) 2017 Arasan Chip Systems Inc.\n+ * Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).\n+ *\n+ * Based on Arasan Driver (sdhci-pci-arasan.c)\n+ * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with integrated phy.\n+ */\n+#include <linux/bitfield.h>\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/iopoll.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/phy/phy.h>\n+#include <linux/platform_device.h>\n+\n+/* Arasan eMMC 5.1 - PHY configuration registers */\n+#define CAP_REG_IN_S1_LSB\t\t0x00\n+#define CAP_REG_IN_S1_MSB\t\t0x04\n+#define PHY_CTRL_1\t\t\t0x38\n+#define PHY_CTRL_2\t\t\t0x3C\n+#define PHY_CTRL_3\t\t\t0x40\n+#define STATUS\t\t\t\t0x50\n+\n+#define DLL_ENBL\tBIT(26)\n+#define RTRIM_EN\tBIT(21)\n+#define PDB_ENBL\tBIT(23)\n+#define RETB_ENBL\tBIT(1)\n+\n+#define REN_STRB\tBIT(27)\n+#define REN_CMD\t\tBIT(12)\n+#define REN_DAT0\tBIT(13)\n+#define REN_DAT1\tBIT(14)\n+#define REN_DAT2\tBIT(15)\n+#define REN_DAT3\tBIT(16)\n+#define REN_DAT4\tBIT(17)\n+#define REN_DAT5\tBIT(18)\n+#define REN_DAT6\tBIT(19)\n+#define REN_DAT7\tBIT(20)\n+#define REN_CMD_EN\t(REN_CMD | REN_DAT0 | REN_DAT1 | REN_DAT2 | \\\n+\t\tREN_DAT3 | REN_DAT4 | REN_DAT5 | REN_DAT6 | REN_DAT7)\n+\n+/* Pull-UP Enable on CMD Line */\n+#define PU_CMD\t\tBIT(3)\n+#define PU_DAT0\t\tBIT(4)\n+#define PU_DAT1\t\tBIT(5)\n+#define PU_DAT2\t\tBIT(6)\n+#define PU_DAT3\t\tBIT(7)\n+#define PU_DAT4\t\tBIT(8)\n+#define PU_DAT5\t\tBIT(9)\n+#define PU_DAT6\t\tBIT(10)\n+#define PU_DAT7\t\tBIT(11)\n+#define PU_CMD_EN (PU_CMD | PU_DAT0 | PU_DAT1 | PU_DAT2 | PU_DAT3 | \\\n+\t\tPU_DAT4 | PU_DAT5 | PU_DAT6 | PU_DAT7)\n+\n+/* Selection value for the optimum delay from 1-32 output tap lines */\n+#define OTAP_DLY\t0x02\n+/* DLL charge pump current trim default [1000] */\n+#define DLL_TRM_ICP\t0x08\n+/* Select the frequency range of DLL Operation */\n+#define FRQ_SEL\t0x01\n+\n+#define OTAP_SEL_MASK\t\tGENMASK(10, 7)\n+#define DLL_TRM_MASK\t\tGENMASK(25, 22)\n+#define DLL_FRQSEL_MASK\t\tGENMASK(27, 25)\n+\n+#define OTAP_SEL(x)\t\t(FIELD_PREP(OTAP_SEL_MASK, x) | OTAPDLY_EN)\n+#define DLL_TRM(x)\t\t(FIELD_PREP(DLL_TRM_MASK, x) | DLL_ENBL)\n+#define DLL_FRQSEL(x)\tFIELD_PREP(DLL_FRQSEL_MASK, x)\n+\n+#define OTAPDLY_EN\tBIT(11)\n+\n+#define SEL_DLY_RXCLK\tBIT(18)\n+#define SEL_DLY_TXCLK\tBIT(19)\n+\n+#define CALDONE_MASK\t0x40\n+#define DLL_RDY_MASK\t0x1\n+#define MAX_CLK_BUF0\tBIT(20)\n+#define MAX_CLK_BUF1\tBIT(21)\n+#define MAX_CLK_BUF2\tBIT(22)\n+\n+#define CLK_MULTIPLIER\t0xC008E\n+#define POLL_TIMEOUT_MS\t3000\n+#define POLL_DELAY_US\t100\n+\n+struct axiado_emmc_phy {\n+\tvoid __iomem *reg_base;\n+\tstruct device *dev;\n+};\n+\n+static int axiado_emmc_phy_init(struct phy *phy)\n+{\n+\tstruct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);\n+\tstruct device *dev = ax_phy->dev;\n+\tu32 val;\n+\tint ret;\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_1);\n+\twritel(val | RETB_ENBL | RTRIM_EN, ax_phy->reg_base + PHY_CTRL_1);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_3);\n+\twritel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);\n+\n+\tret = readl_poll_timeout(ax_phy->reg_base + STATUS, val,\n+\t\t\t\t val & CALDONE_MASK, POLL_DELAY_US,\n+\t\t\t\t POLL_TIMEOUT_MS * 1000);\n+\tif (ret) {\n+\t\tdev_err(dev, \"PHY calibration timeout\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_1);\n+\twritel(val | REN_CMD_EN | PU_CMD_EN, ax_phy->reg_base + PHY_CTRL_1);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_2);\n+\twritel(val | REN_STRB, ax_phy->reg_base + PHY_CTRL_2);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_3);\n+\twritel(val | MAX_CLK_BUF0 | MAX_CLK_BUF1 | MAX_CLK_BUF2,\n+\t ax_phy->reg_base + PHY_CTRL_3);\n+\n+\twritel(CLK_MULTIPLIER, ax_phy->reg_base + CAP_REG_IN_S1_MSB);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_3);\n+\twritel(val | SEL_DLY_RXCLK | SEL_DLY_TXCLK,\n+\t ax_phy->reg_base + PHY_CTRL_3);\n+\n+\treturn 0;\n+}\n+\n+static int axiado_emmc_phy_power_on(struct phy *phy)\n+{\n+\tstruct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);\n+\tstruct device *dev = ax_phy->dev;\n+\tu32 val;\n+\tint ret;\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_1);\n+\twritel(val | RETB_ENBL, ax_phy->reg_base + PHY_CTRL_1);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_3);\n+\twritel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_2);\n+\twritel(val | OTAP_SEL(OTAP_DLY), ax_phy->reg_base + PHY_CTRL_2);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_1);\n+\twritel(val | DLL_TRM(DLL_TRM_ICP), ax_phy->reg_base + PHY_CTRL_1);\n+\n+\tval = readl(ax_phy->reg_base + PHY_CTRL_3);\n+\twritel(val | DLL_FRQSEL(FRQ_SEL), ax_phy->reg_base + PHY_CTRL_3);\n+\n+\tret = read_poll_timeout(readl, val, val & DLL_RDY_MASK, POLL_DELAY_US,\n+\t\t\t\tPOLL_TIMEOUT_MS * 1000, false,\n+\t\t\t\tax_phy->reg_base + STATUS);\n+\tif (ret) {\n+\t\tdev_err(dev, \"DLL ready timeout\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct phy_ops axiado_emmc_phy_ops = {\n+\t.init = axiado_emmc_phy_init,\n+\t.power_on = axiado_emmc_phy_power_on,\n+\t.owner = THIS_MODULE,\n+};\n+\n+static const struct of_device_id axiado_emmc_phy_of_match[] = {\n+\t{ .compatible = \"axiado,ax3000-emmc-phy\" },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, axiado_emmc_phy_of_match);\n+\n+static int axiado_emmc_phy_probe(struct platform_device *pdev)\n+{\n+\tstruct axiado_emmc_phy *ax_phy;\n+\tstruct phy_provider *phy_provider;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct phy *generic_phy;\n+\n+\tif (!dev->of_node)\n+\t\treturn -ENODEV;\n+\n+\tax_phy = devm_kzalloc(dev, sizeof(*ax_phy), GFP_KERNEL);\n+\tif (!ax_phy)\n+\t\treturn -ENOMEM;\n+\n+\tax_phy->reg_base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(ax_phy->reg_base))\n+\t\treturn PTR_ERR(ax_phy->reg_base);\n+\n+\tax_phy->dev = dev;\n+\n+\tgeneric_phy = devm_phy_create(dev, dev->of_node, &axiado_emmc_phy_ops);\n+\tif (IS_ERR(generic_phy))\n+\t\treturn dev_err_probe(dev, PTR_ERR(generic_phy),\n+\t\t\t\t \"failed to create PHY\\n\");\n+\n+\tphy_set_drvdata(generic_phy, ax_phy);\n+\tphy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);\n+\n+\treturn PTR_ERR_OR_ZERO(phy_provider);\n+}\n+\n+static struct platform_driver axiado_emmc_phy_driver = {\n+\t.probe = axiado_emmc_phy_probe,\n+\t.driver = {\n+\t\t.name = \"axiado-emmc-phy\",\n+\t\t.of_match_table = axiado_emmc_phy_of_match,\n+\t},\n+};\n+module_platform_driver(axiado_emmc_phy_driver);\n+\n+MODULE_DESCRIPTION(\"AX3000 eMMC PHY Driver\");\n+MODULE_AUTHOR(\"Axiado Corporation\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v2", "2/4" ] }