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GET /api/patches/2194417/?format=api
{ "id": 2194417, "url": "http://patchwork.ozlabs.org/api/patches/2194417/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-8-festevam@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208212624.3413494-8-festevam@gmail.com>", "list_archive_url": null, "date": "2026-02-08T21:26:24", "name": "[v2,7/7] omega4-rv1103b: Add the initial support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "cf0cd7405ac5028fa554f872a15c5e8dcdde6c3e", "submitter": { "id": 6978, "url": "http://patchwork.ozlabs.org/api/people/6978/?format=api", "name": "Fabio Estevam", "email": "festevam@gmail.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-8-festevam@gmail.com/mbox/", "series": [ { "id": 491441, "url": "http://patchwork.ozlabs.org/api/series/491441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491441", "date": "2026-02-08T21:26:17", "name": "ARM: Add RV1103B Omega4 board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491441/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194417/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194417/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"kever.yang@rock-chips.com", "Cc": "trini@konsulko.com, jonas@kwiboo.se, u-boot@lists.denx.de,\n Fabio Estevam <festevam@nabladev.com>", "Subject": "[PATCH v2 7/7] omega4-rv1103b: Add the initial support", "Date": "Sun, 8 Feb 2026 18:26:24 -0300", "Message-Id": "<20260208212624.3413494-8-festevam@gmail.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208212624.3413494-1-festevam@gmail.com>", "References": "<20260208212624.3413494-1-festevam@gmail.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Fabio Estevam <festevam@nabladev.com>\n\nAdd the initial support for Onion's Omega4 RV1103B board.\n\nIt boots from the SPI NAND.\n\nTested the boot of a 6.6 OpenWRT kernel and also a 6.19-rc8 mainline\nkernel.\n\nSigned-off-by: Fabio Estevam <festevam@nabladev.com>\n---\nChanges since v1:\n- Only adapted to the correct SoC name: RV1103B instead of RV1103.\n\n arch/arm/include/asm/arch-rv1103b/boot0.h | 11 ++\n arch/arm/mach-rockchip/Kconfig | 14 ++\n arch/arm/mach-rockchip/Makefile | 1 +\n arch/arm/mach-rockchip/rv1103b/Kconfig | 23 +++\n arch/arm/mach-rockchip/rv1103b/Makefile | 12 ++\n arch/arm/mach-rockchip/rv1103b/boot0.h | 5 +\n arch/arm/mach-rockchip/rv1103b/clk_rv1103b.c | 32 +++++\n arch/arm/mach-rockchip/rv1103b/rv1103b.c | 133 ++++++++++++++++++\n .../mach-rockchip/rv1103b/syscon_rv1103b.c | 19 +++\n board/onion/omega4_rv1103b/Kconfig | 12 ++\n board/onion/omega4_rv1103b/MAINTAINERS | 6 +\n board/onion/omega4_rv1103b/Makefile | 7 +\n board/onion/omega4_rv1103b/omega4_rv1103b.c | 19 +++\n board/onion/omega4_rv1103b/omega4_rv1103b.env | 5 +\n configs/omega4-rv1103b_defconfig | 82 +++++++++++\n doc/board/index.rst | 1 +\n doc/board/onion/index.rst | 9 ++\n doc/board/onion/omega4-rv1103b.rst | 56 ++++++++\n include/configs/omega4_rv1103b.h | 11 ++\n include/configs/rv1103b_common.h | 14 ++\n 20 files changed, 472 insertions(+)\n create mode 100644 arch/arm/include/asm/arch-rv1103b/boot0.h\n create mode 100644 arch/arm/mach-rockchip/rv1103b/Kconfig\n create mode 100644 arch/arm/mach-rockchip/rv1103b/Makefile\n create mode 100644 arch/arm/mach-rockchip/rv1103b/boot0.h\n create mode 100644 arch/arm/mach-rockchip/rv1103b/clk_rv1103b.c\n create mode 100644 arch/arm/mach-rockchip/rv1103b/rv1103b.c\n create mode 100644 arch/arm/mach-rockchip/rv1103b/syscon_rv1103b.c\n create mode 100644 board/onion/omega4_rv1103b/Kconfig\n create mode 100644 board/onion/omega4_rv1103b/MAINTAINERS\n create mode 100644 board/onion/omega4_rv1103b/Makefile\n create mode 100644 board/onion/omega4_rv1103b/omega4_rv1103b.c\n create mode 100644 board/onion/omega4_rv1103b/omega4_rv1103b.env\n create mode 100644 configs/omega4-rv1103b_defconfig\n create mode 100644 doc/board/onion/index.rst\n create mode 100644 doc/board/onion/omega4-rv1103b.rst\n create mode 100644 include/configs/omega4_rv1103b.h\n create mode 100644 include/configs/rv1103b_common.h", "diff": "diff --git a/arch/arm/include/asm/arch-rv1103b/boot0.h b/arch/arm/include/asm/arch-rv1103b/boot0.h\nnew file mode 100644\nindex 000000000000..2e78b074ade8\n--- /dev/null\n+++ b/arch/arm/include/asm/arch-rv1103b/boot0.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd\n+ */\n+\n+#ifndef __ASM_ARCH_BOOT0_H__\n+#define __ASM_ARCH_BOOT0_H__\n+\n+#include <asm/arch-rockchip/boot0.h>\n+\n+#endif\ndiff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig\nindex 92bb4aa62f11..c1faeb974328 100644\n--- a/arch/arm/mach-rockchip/Kconfig\n+++ b/arch/arm/mach-rockchip/Kconfig\n@@ -487,6 +487,19 @@ config ROCKCHIP_RK3588\n \t SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0, PCIe 3.0, SATA 3, Ethernet,\n \t SDIO3.0 I2C, UART, SPI, GPIO and PWM.\n \n+config ROCKCHIP_RV1103B\n+\tbool \"Support Rockchip RV1103B\"\n+\tselect CPU_V7A\n+\tselect SPL_ARMV7_SET_CORTEX_SMPEN\n+\tselect SUPPORT_SPL\n+\tselect SPL\n+\timply ROCKCHIP_COMMON_BOARD\n+\n+\thelp\n+\t The Rockchip RV1103B is an ARM-based SoC with a single Cortex-A7\n+\t 32-bit core which integrates NEON and FPU.\n+\t It contains a built-in NPU for AI related applications.\n+\n config ROCKCHIP_RV1108\n \tbool \"Support Rockchip RV1108\"\n \tselect CPU_V7A\n@@ -749,6 +762,7 @@ source \"arch/arm/mach-rockchip/rk3528/Kconfig\"\n source \"arch/arm/mach-rockchip/rk3568/Kconfig\"\n source \"arch/arm/mach-rockchip/rk3576/Kconfig\"\n source \"arch/arm/mach-rockchip/rk3588/Kconfig\"\n+source \"arch/arm/mach-rockchip/rv1103b/Kconfig\"\n source \"arch/arm/mach-rockchip/rv1108/Kconfig\"\n source \"arch/arm/mach-rockchip/rv1126/Kconfig\"\n \ndiff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile\nindex 06fb527b21a0..7bbb1697836c 100644\n--- a/arch/arm/mach-rockchip/Makefile\n+++ b/arch/arm/mach-rockchip/Makefile\n@@ -46,6 +46,7 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/\n obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/\n obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/\n obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/\n+obj-$(CONFIG_ROCKCHIP_RV1103B) += rv1103b/\n obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/\n obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/\n \ndiff --git a/arch/arm/mach-rockchip/rv1103b/Kconfig b/arch/arm/mach-rockchip/rv1103b/Kconfig\nnew file mode 100644\nindex 000000000000..6b5f5b0b9e14\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/Kconfig\n@@ -0,0 +1,23 @@\n+if ROCKCHIP_RV1103B\n+\n+\n+config TARGET_OMEGA4_RV1103B\n+\tbool \"OMEGA4_RV1103B\"\n+\thelp\n+\t Support Onion's Omega4 RV1103B board.\n+\n+config ROCKCHIP_BOOT_MODE_REG\n+\tdefault 0x20160200\n+\n+config ROCKCHIP_STIMER_BASE\n+\tdefault 0x20500000\n+\n+config SYS_SOC\n+\tdefault \"rv1103b\"\n+\n+config SYS_MALLOC_F_LEN\n+\tdefault 0x400\n+\n+source \"board/onion/omega4_rv1103b/Kconfig\"\n+\n+endif\ndiff --git a/arch/arm/mach-rockchip/rv1103b/Makefile b/arch/arm/mach-rockchip/rv1103b/Makefile\nnew file mode 100644\nindex 000000000000..2f34853adac5\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/Makefile\n@@ -0,0 +1,12 @@\n+#\n+# (C) Copyright 2016 Rockchip Electronics Co., Ltd\n+#\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+\n+obj-y += rv1103b.o\n+obj-y += clk_rv1103b.o\n+\n+ifndef CONFIG_XPL_BUILD\n+obj-y += syscon_rv1103b.o\n+endif\ndiff --git a/arch/arm/mach-rockchip/rv1103b/boot0.h b/arch/arm/mach-rockchip/rv1103b/boot0.h\nnew file mode 100644\nindex 000000000000..466ab0e80770\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/boot0.h\n@@ -0,0 +1,5 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/* Dummy boot0.h for RV1103B — SoC does not require special boot0 setup. */\n+#ifndef __ASM_ARCH_BOOT0_H__\n+#define __ASM_ARCH_BOOT0_H__\n+#endif\ndiff --git a/arch/arm/mach-rockchip/rv1103b/clk_rv1103b.c b/arch/arm/mach-rockchip/rv1103b/clk_rv1103b.c\nnew file mode 100644\nindex 000000000000..2bcbb08537e8\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/clk_rv1103b.c\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n+ * Author: Andy Yan <andy.yan@rock-chips.com>\n+ */\n+\n+#include <dm.h>\n+#include <syscon.h>\n+#include <asm/arch-rockchip/clock.h>\n+#include <asm/arch-rockchip/cru_rv1103b.h>\n+#include <linux/err.h>\n+\n+int rockchip_get_clk(struct udevice **devp)\n+{\n+\treturn uclass_get_device_by_driver(UCLASS_CLK,\n+\t\t\tDM_DRIVER_GET(clk_rv1103b), devp);\n+}\n+\n+void *rockchip_get_cru(void)\n+{\n+\tstruct rv1103b_clk_priv *priv;\n+\tstruct udevice *dev;\n+\tint ret;\n+\n+\tret = rockchip_get_clk(&dev);\n+\tif (ret)\n+\t\treturn ERR_PTR(ret);\n+\n+\tpriv = dev_get_priv(dev);\n+\n+\treturn priv->cru;\n+}\ndiff --git a/arch/arm/mach-rockchip/rv1103b/rv1103b.c b/arch/arm/mach-rockchip/rv1103b/rv1103b.c\nnew file mode 100644\nindex 000000000000..a7ff1934f7db\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/rv1103b.c\n@@ -0,0 +1,133 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+// Copyright (c) 2024 Rockchip Electronics Co., Ltd\n+\n+#include <dm.h>\n+#include <spl.h>\n+#include <asm/io.h>\n+#include <image.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define PERI_CRU_BASE\t\t\t0x20000000\n+#define PERICRU_PERISOFTRST_CON10\t0x0a28\n+\n+#define PMU0_CRU_BASE\t\t\t0x20070000\n+#define PMUCRU_PMUSOFTRST_CON02\t\t0x0a08\n+\n+#define GRF_SYS_BASE\t\t\t0x20150000\n+#define GRF_SYS_HPMCU_CACHE_MISC\t0x0214\n+\n+#define GPIO0_IOC_BASE\t\t\t0x201B0000\n+#define GPIO0A_IOMUX_SEL_H\t\t0x04\n+#define GPIO0_BASE\t\t\t0x20520000\n+#define GPIO_SWPORT_DR_L\t\t0x00\n+#define GPIO_SWPORT_DDR_L\t\t0x08\n+\n+#define GPIO1_IOC_BASE\t\t\t0x20170000\n+#define GPIO1A_IOMUX_SEL_0\t\t0x20\n+#define GPIO1A_IOMUX_SEL_1_0\t\t0x24\n+#define GPIO1A_IOMUX_SEL_1_1\t\t0x10024\n+#define GPIO1B_IOMUX_SEL_0\t\t0x10028\n+#define GPIO1B_IOMUX_SEL_1\t\t0x1002c\n+#define GPIO1_IOC_GPIO1A_PULL_0\t\t0x210\n+#define GPIO1_IOC_GPIO1A_PULL_1\t\t0x10210\n+#define GPIO1_IOC_GPIO1B_PULL\t\t0x10214\n+#define GPIO1_IOC_JTAG_M2_CON\t\t0x10810\n+\n+#define GPIO2_IOC_BASE\t\t\t0x20840000\n+#define GPIO2A_IOMUX_SEL_1_1\t\t0x44\n+\n+#define SGRF_SYS_BASE\t\t\t0x20250000\n+#define SGRF_SYS_SOC_CON2\t\t0x0008\n+#define SGRF_SYS_SOC_CON3\t\t0x000c\n+#define SGRF_SYS_OTP_CON\t\t0x0018\n+#define FIREWALL_CON0\t\t\t0x0020\n+#define FIREWALL_CON1\t\t\t0x0024\n+#define FIREWALL_CON2\t\t\t0x0028\n+#define FIREWALL_CON3\t\t\t0x002c\n+#define FIREWALL_CON4\t\t\t0x0030\n+#define FIREWALL_CON5\t\t\t0x0034\n+#define FIREWALL_CON7\t\t\t0x003c\n+#define SGRF_SYS_HPMCU_BOOT_DDR\t\t0x0080\n+\n+#define SGRF_PMU_BASE\t\t\t0x20260000\n+#define SGRF_PMU_SOC_CON0\t\t0x0000\n+#define SGRF_PMU_PMUMCU_BOOT_ADDR\t0x0020\n+\n+#define SYS_GRF_BASE\t\t\t0x20150000\n+#define GRF_SYS_PERI_CON2\t\t0x08\n+#define GRF_SYS_USBPHY_CON0\t\t0x50\n+\n+#define TOP_CRU_BASE\t\t\t0x20060000\n+#define TOPCRU_CRU_GLB_RST_CON\t\t0xc10\n+\n+#define USBPHY_APB_BASE\t\t\t0x20e10000\n+#define USBPHY_FSLS_DIFF_RECEIVER\t0x0100\n+\n+#define RV1103B_WDT_BASE\t\t\t0x208d0000\n+#define RV1103B_WDT_CR\t\t\t0x00\n+\n+void board_debug_uart_init(void)\n+{\n+\t/* No need to change uart */\n+}\n+\n+#ifdef CONFIG_SPL_BUILD\n+void rockchip_stimer_init(void)\n+{\n+\t/* If Timer already enabled, don't re-init it */\n+\tu32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);\n+\n+\tif (reg & 0x1)\n+\t\treturn;\n+\twritel(0x00010000, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);\n+\n+\tasm volatile(\"mcr p15, 0, %0, c14, c0, 0\" : : \"r\"(CONFIG_COUNTER_FREQUENCY));\n+\twritel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);\n+\twritel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);\n+\twritel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);\n+}\n+#endif\n+\n+#ifndef CONFIG_TPL_BUILD\n+int arch_cpu_init(void)\n+{\n+\t/* Stop any watchdog left running by BootROM/Boot1. */\n+\twritel(0, RV1103B_WDT_BASE + RV1103B_WDT_CR);\n+\n+#if defined(CONFIG_SPL_BUILD)\n+\t/* Set all devices to Non-secure */\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON0);\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON1);\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON2);\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON3);\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON4);\n+\twritel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON5);\n+\twritel(0x01f00000, SGRF_SYS_BASE + FIREWALL_CON7);\n+\t/* Set OTP to none secure mode */\n+\twritel(0x00020000, SGRF_SYS_BASE + SGRF_SYS_OTP_CON);\n+\n+\t/* no-secure WDT reset output will reset SoC system. */\n+\twritel(0x00010001, SYS_GRF_BASE + GRF_SYS_PERI_CON2);\n+\t/* secure WDT reset output will reset SoC system. */\n+\twritel(0x00010001, SGRF_SYS_BASE + SGRF_SYS_SOC_CON2);\n+\t/*\n+\t * enable tsadc trigger global reset and select first reset.\n+\t * enable global reset and wdt trigger pmu reset.\n+\t * select first reset trigger pmu reset.\n+\t */\n+\twritel(0x0000ffdf, TOP_CRU_BASE + TOPCRU_CRU_GLB_RST_CON);\n+\n+\t/*\n+\t * Set the USB2 PHY in suspend mode and turn off the\n+\t * USB2 PHY FS/LS differential receiver to save power:\n+\t * VCC1V8_USB : reduce 3.8 mA\n+\t * VDD_0V9 : reduce 4.4 mA\n+\t */\n+\twritel(0x01ff01d1, SYS_GRF_BASE + GRF_SYS_USBPHY_CON0);\n+\twritel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);\n+#endif\n+\n+\treturn 0;\n+}\n+#endif\ndiff --git a/arch/arm/mach-rockchip/rv1103b/syscon_rv1103b.c b/arch/arm/mach-rockchip/rv1103b/syscon_rv1103b.c\nnew file mode 100644\nindex 000000000000..545b4d8ebe12\n--- /dev/null\n+++ b/arch/arm/mach-rockchip/rv1103b/syscon_rv1103b.c\n@@ -0,0 +1,19 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n+ */\n+\n+#include <dm.h>\n+#include <syscon.h>\n+#include <asm/arch-rockchip/clock.h>\n+\n+static const struct udevice_id rv1103b_syscon_ids[] = {\n+\t{ .compatible = \"rockchip,rv1103b-grf\", .data = ROCKCHIP_SYSCON_GRF },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(syscon_rv1103b) = {\n+\t.name = \"rv1103b_syscon\",\n+\t.id = UCLASS_SYSCON,\n+\t.of_match = rv1103b_syscon_ids,\n+};\ndiff --git a/board/onion/omega4_rv1103b/Kconfig b/board/onion/omega4_rv1103b/Kconfig\nnew file mode 100644\nindex 000000000000..43b126c20e9c\n--- /dev/null\n+++ b/board/onion/omega4_rv1103b/Kconfig\n@@ -0,0 +1,12 @@\n+if TARGET_OMEGA4_RV1103B\n+\n+config SYS_BOARD\n+\tdefault \"omega4_rv1103b\"\n+\n+config SYS_VENDOR\n+\tdefault \"onion\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"omega4_rv1103b\"\n+\n+endif\ndiff --git a/board/onion/omega4_rv1103b/MAINTAINERS b/board/onion/omega4_rv1103b/MAINTAINERS\nnew file mode 100644\nindex 000000000000..53d774535bdd\n--- /dev/null\n+++ b/board/onion/omega4_rv1103b/MAINTAINERS\n@@ -0,0 +1,6 @@\n+OMEGA4 RV1103B\n+M: Fabio Estevam <festevam@nabladev.com>\n+S: Maintained\n+F: board/onion/omega4_rv1103b\n+F: include/configs/omega4_rv1103b.h\n+F: configs/omega4-rv1103b_defconfig\ndiff --git a/board/onion/omega4_rv1103b/Makefile b/board/onion/omega4_rv1103b/Makefile\nnew file mode 100644\nindex 000000000000..afa0a7f7a932\n--- /dev/null\n+++ b/board/onion/omega4_rv1103b/Makefile\n@@ -0,0 +1,7 @@\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+# Copyright 2026 Fabio Estevam <festevam@nabladev.com>\n+#\n+\n+obj-y\t+= omega4_rv1103b.o\ndiff --git a/board/onion/omega4_rv1103b/omega4_rv1103b.c b/board/onion/omega4_rv1103b/omega4_rv1103b.c\nnew file mode 100644\nindex 000000000000..9bdec3c396a8\n--- /dev/null\n+++ b/board/onion/omega4_rv1103b/omega4_rv1103b.c\n@@ -0,0 +1,19 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+//\n+// Copyright 2026 Fabio Estevam <festevam@nabladev.com>\n+\n+#include <asm/global_data.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = SZ_256M;\n+\n+\treturn 0;\n+}\n+\n+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)\n+{\n+\treturn gd->ram_top;\n+}\ndiff --git a/board/onion/omega4_rv1103b/omega4_rv1103b.env b/board/onion/omega4_rv1103b/omega4_rv1103b.env\nnew file mode 100644\nindex 000000000000..7ed232cab916\n--- /dev/null\n+++ b/board/onion/omega4_rv1103b/omega4_rv1103b.env\n@@ -0,0 +1,5 @@\n+kernel_addr_r=0x00800000\n+fdt_addr_r=0x02000000\n+ramdisk_addr_r=0x04000000\n+bootargs=console=ttyS0,115200 mtdparts=spi1.0:256K(env),1M@256K(idblock),1M(uboot),8M(boot),-(ubi) ro rootwait ubi.mtd=ubi ubi.block=0,rootfs root=/dev/ubiblock0_0 rootfstype=squashfs\n+bootcmd=mtd read spi-nand0 0x04000000 0x240000 0x800000;imxtract 0x04000000 kernel 0x00800000; imxtract 0x04000000 fdt 0x02000000; bootz 0x00800000 - 0x02000000\ndiff --git a/configs/omega4-rv1103b_defconfig b/configs/omega4-rv1103b_defconfig\nnew file mode 100644\nindex 000000000000..b1e8ede1cf6e\n--- /dev/null\n+++ b/configs/omega4-rv1103b_defconfig\n@@ -0,0 +1,82 @@\n+CONFIG_ARM=y\n+CONFIG_SKIP_LOWLEVEL_INIT=y\n+CONFIG_COUNTER_FREQUENCY=24000000\n+CONFIG_SYS_ARCH_TIMER=y\n+CONFIG_ARCH_ROCKCHIP=y\n+CONFIG_TEXT_BASE=0x00200000\n+CONFIG_SYS_MALLOC_F_LEN=0x80000\n+CONFIG_SPL_LIBCOMMON_SUPPORT=y\n+CONFIG_SPL_LIBGENERIC_SUPPORT=y\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00400000\n+CONFIG_SF_DEFAULT_SPEED=24000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"rv1103b-omega4\"\n+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000\n+CONFIG_ROCKCHIP_RV1103B=y\n+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y\n+CONFIG_ROCKCHIP_EXTERNAL_TPL=y\n+CONFIG_SPL_SERIAL=y\n+CONFIG_TARGET_OMEGA4_RV1103B=y\n+CONFIG_SYS_BOOTM_LEN=0x04000000\n+CONFIG_SYS_LOAD_ADDR=0x00008000\n+CONFIG_SF_DEFAULT_BUS=1\n+CONFIG_DEBUG_UART_BASE=0x20540000\n+CONFIG_DEBUG_UART_CLOCK=24000000\n+# CONFIG_DEBUG_UART_BOARD_INIT is not set\n+CONFIG_SPL_SPI_FLASH_SUPPORT=y\n+CONFIG_SPL_SPI=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_FIT=y\n+CONFIG_FIT_SIGNATURE=y\n+CONFIG_FIT_CIPHER=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_FIT_BEST_MATCH=y\n+CONFIG_LEGACY_IMAGE_FORMAT=y\n+CONFIG_BOOTDELAY=1\n+# CONFIG_DISPLAY_CPUINFO is not set\n+CONFIG_SPL_NO_BSS_LIMIT=y\n+CONFIG_SPL_MTD=y\n+CONFIG_SPL_SPI_NAND_LOAD=y\n+CONFIG_SYS_SPI_U_BOOT_OFFS=0x140000\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_SPI=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_TIME=y\n+CONFIG_SPL_OF_CONTROL=y\n+CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n+CONFIG_NO_NET=y\n+CONFIG_SPL_DM_SEQ_ALIAS=y\n+CONFIG_REGMAP=y\n+CONFIG_SPL_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_SPL_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_SPL_CLK=y\n+CONFIG_ROCKCHIP_GPIO=y\n+CONFIG_SYS_I2C_ROCKCHIP=y\n+# CONFIG_MMC is not set\n+CONFIG_DM_MTD=y\n+CONFIG_MTD_SPI_NAND=y\n+CONFIG_SPI_FLASH_SFDP_SUPPORT=y\n+CONFIG_SPI_FLASH_GIGADEVICE=y\n+CONFIG_SPI_FLASH_WINBOND=y\n+CONFIG_SPI_FLASH_XTX=y\n+CONFIG_SPI_FLASH_MTD=y\n+CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n+CONFIG_PINCTRL_ROCKCHIP_RV1103B=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DEBUG_UART_SHIFT=2\n+CONFIG_SYS_NS16550_MEM32=y\n+CONFIG_ROCKCHIP_SFC=y\n+CONFIG_SYSRESET=y\n+# CONFIG_RSA is not set\n+# CONFIG_SPL_SHA1 is not set\n+# CONFIG_SPL_SHA256 is not set\n+CONFIG_LZMA=y\n+CONFIG_SPL_LZMA=y\n+CONFIG_ERRNO_STR=y\ndiff --git a/doc/board/index.rst b/doc/board/index.rst\nindex 7870f1bc2461..d859f8a22bfe 100644\n--- a/doc/board/index.rst\n+++ b/doc/board/index.rst\n@@ -45,6 +45,7 @@ Board-specific doc\n motorola/index\n nvidia/index\n nxp/index\n+ onion/index\n openpiton/index\n ouya/index\n pegatron/index\ndiff --git a/doc/board/onion/index.rst b/doc/board/onion/index.rst\nnew file mode 100644\nindex 000000000000..2e106c8b7734\n--- /dev/null\n+++ b/doc/board/onion/index.rst\n@@ -0,0 +1,9 @@\n+.. SPDX-License-Identifier: GPL-2.0+\n+\n+Onion\n+=====\n+\n+.. toctree::\n+ :maxdepth: 2\n+\n+ omega4-rv1103b\ndiff --git a/doc/board/onion/omega4-rv1103b.rst b/doc/board/onion/omega4-rv1103b.rst\nnew file mode 100644\nindex 000000000000..41c64f40d6c4\n--- /dev/null\n+++ b/doc/board/onion/omega4-rv1103b.rst\n@@ -0,0 +1,56 @@\n+.. SPDX-License-Identifier: GPL-2.0+\n+\n+Onion Omega4 RV1103B board\n+==========================\n+\n+U-Boot for the Onion Omega4 RV1103B board\n+\n+Quick Start\n+-----------\n+\n+- Get the DDR initialization binary\n+- Build U-Boot\n+- Flash U-Boot into the SPI NAND\n+\n+Get the DDR initialization binary\n+---------------------------------\n+\n+.. code-block:: bash\n+\n+ $ git clone https://github.com/rockchip-linux/rkbin.git\n+\n+The RV1103B DDR initialization is located at rkbin/bin/rv11/rv1103bb_ddr_924MHz_v1.05.bin\n+\n+Build U-Boot\n+------------\n+\n+.. code-block:: bash\n+\n+ $ export CROSS_COMPILE=arm-linux-gnueabihf-\n+ $ export ROCKCHIP_TPL=<path-to-rkbin>/bin/rv11/rv1103bb_ddr_924MHz_v1.05.bin\n+ $ make omega4-rv1103b_defconfig\n+ $ make\n+\n+The idbloader-spi.img and u-boot.img are the binaries that need to be flashed\n+into the SPI NAND.\n+\n+Flash U-Boot into the SPI NAND\n+------------------------------\n+\n+Connect the USB OTG and UART console cables from the Omega4 board to\n+the host PC.\n+\n+Press the BOOT button while applying power to the board.\n+\n+The string \"RKUART\" should appear on the console (115200,8N1).\n+\n+Install the rkdeveloptool from https://github.com/rockchip-linux/rkdeveloptool\n+by following the instruction in the README file.\n+\n+.. code-block:: bash\n+\n+ $ sudo ./rkdeveloptool db download.bin\n+ $ sudo ./rkdeveloptool wl 0x200 idbloader.img\n+ $ sudo ./rkdeveloptool wl 0xa00 u-boot.img\n+\n+Power cycle the board and U-Boot output is seen on the console.\ndiff --git a/include/configs/omega4_rv1103b.h b/include/configs/omega4_rv1103b.h\nnew file mode 100644\nindex 000000000000..8430b0b4d091\n--- /dev/null\n+++ b/include/configs/omega4_rv1103b.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#include <configs/rv1103b_common.h>\n+\n+#endif\ndiff --git a/include/configs/rv1103b_common.h b/include/configs/rv1103b_common.h\nnew file mode 100644\nindex 000000000000..8e970d710514\n--- /dev/null\n+++ b/include/configs/rv1103b_common.h\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n+ */\n+#ifndef __CONFIG_RV1103B_COMMON_H\n+#define __CONFIG_RV1103B_COMMON_H\n+\n+#include \"rockchip-common.h\"\n+#include <config_distro_bootcmd.h>\n+\n+#define CFG_IRAM_BASE\t\t\t0x210f6000\n+#define CFG_SYS_SDRAM_BASE\t\t0x00000000\n+\n+#endif\n", "prefixes": [ "v2", "7/7" ] }