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GET /api/patches/2194412/?format=api
{ "id": 2194412, "url": "http://patchwork.ozlabs.org/api/patches/2194412/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-3-festevam@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208212624.3413494-3-festevam@gmail.com>", "list_archive_url": null, "date": "2026-02-08T21:26:19", "name": "[v2,2/7] pinctrl: rockchip: Add RV1103B support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "4d298734b0b47494c79a51b4e216ec101ca0a9b2", "submitter": { "id": 6978, "url": "http://patchwork.ozlabs.org/api/people/6978/?format=api", "name": "Fabio Estevam", "email": "festevam@gmail.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-3-festevam@gmail.com/mbox/", "series": [ { "id": 491441, "url": "http://patchwork.ozlabs.org/api/series/491441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491441", "date": "2026-02-08T21:26:17", "name": "ARM: Add RV1103B Omega4 board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491441/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194412/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194412/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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"kever.yang@rock-chips.com", "Cc": "trini@konsulko.com, jonas@kwiboo.se, u-boot@lists.denx.de,\n Ye Zhang <ye.zhang@rock-chips.com>, Fabio Estevam <festevam@nabladev.com>", "Subject": "[PATCH v2 2/7] pinctrl: rockchip: Add RV1103B support", "Date": "Sun, 8 Feb 2026 18:26:19 -0300", "Message-Id": "<20260208212624.3413494-3-festevam@gmail.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208212624.3413494-1-festevam@gmail.com>", "References": "<20260208212624.3413494-1-festevam@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Ye Zhang <ye.zhang@rock-chips.com>\n\nAdd pinctrl driver for RV1103.\n\nSigned-off-by: Ye Zhang <ye.zhang@rock-chips.com>\nSigned-off-by: Fabio Estevam <festevam@nabladev.com>\n---\nChanges since v1:\n- Use the original author from Rockchip's vendor U-Boot tree.\n- Use regmap_update_bits()\n- Removed unneeded blank lines.\n- Removed unneeded logging functions.\n\n drivers/pinctrl/rockchip/Makefile | 1 +\n drivers/pinctrl/rockchip/pinctrl-rv1103b.c | 398 +++++++++++++++++++++\n 2 files changed, 399 insertions(+)\n create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1103b.c", "diff": "diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile\nindex e17415e1ca68..2bbee66bd3ca 100644\n--- a/drivers/pinctrl/rockchip/Makefile\n+++ b/drivers/pinctrl/rockchip/Makefile\n@@ -18,5 +18,6 @@ obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o\n obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o\n obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o\n obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o\n+obj-$(CONFIG_ROCKCHIP_RV1103B) += pinctrl-rv1103b.o\n obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o\n obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o\ndiff --git a/drivers/pinctrl/rockchip/pinctrl-rv1103b.c b/drivers/pinctrl/rockchip/pinctrl-rv1103b.c\nnew file mode 100644\nindex 000000000000..fb946b036661\n--- /dev/null\n+++ b/drivers/pinctrl/rockchip/pinctrl-rv1103b.c\n@@ -0,0 +1,398 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd\n+ */\n+\n+#include <dm.h>\n+#include <log.h>\n+#include <dm/pinctrl.h>\n+#include <regmap.h>\n+#include <syscon.h>\n+#include <linux/bitops.h>\n+\n+#include \"pinctrl-rockchip.h\"\n+\n+static int rv1103b_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)\n+{\n+\tstruct rockchip_pinctrl_priv *priv = bank->priv;\n+\tint iomux_num = (pin / 8);\n+\tstruct regmap *regmap;\n+\tu32 data, rmask;\n+\tint reg, mask;\n+\tu8 bit;\n+\n+\tif (bank->bank_num == 2 && pin >= 12)\n+\t\treturn 0;\n+\n+\tregmap = priv->regmap_base;\n+\treg = bank->iomux[iomux_num].offset;\n+\tif ((pin % 8) >= 4)\n+\t\treg += 0x4;\n+\tbit = (pin % 4) * 4;\n+\tmask = 0xf;\n+\n+\tif (bank->recalced_mask & BIT(pin))\n+\t\trockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);\n+\tdata = (mask << (bit + 16));\n+\trmask = data | (data >> 16);\n+\tdata |= (mux & mask) << bit;\n+\n+\treturn regmap_update_bits(regmap, reg, rmask, data);\n+}\n+\n+#define RV1103_DRV_BITS_PER_PIN\t\t8\n+#define RV1103_DRV_PINS_PER_REG\t\t2\n+#define RV1103_DRV_GPIO0_A_OFFSET\t\t0x40100\n+#define RV1103_DRV_GPIO0_B_OFFSET\t\t0x50110\n+#define RV1103_DRV_GPIO1_A01_OFFSET\t\t0x140\n+#define RV1103_DRV_GPIO1_A67_OFFSET\t\t0x1014C\n+#define RV1103_DRV_GPIO2_OFFSET\t\t0x30180\n+#define RV1103_DRV_GPIO2_SARADC_OFFSET\t\t0x3080C\n+\n+static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t int pin_num, struct regmap **regmap,\n+\t\t\t\t int *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl_priv *priv = bank->priv;\n+\tint ret = 0;\n+\n+\t*regmap = priv->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103_DRV_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103_DRV_GPIO0_B_OFFSET - 0x10;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103_DRV_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103_DRV_GPIO1_A67_OFFSET - 0xc;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103_DRV_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103_DRV_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 10;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tprintf(\"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103_DRV_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103_DRV_PINS_PER_REG;\n+\t*bit *= RV1103_DRV_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n+static int rv1103b_set_drive(struct rockchip_pin_bank *bank,\n+\t\t\t int pin_num, int strength)\n+{\n+\tstruct regmap *regmap;\n+\tint reg, ret, i;\n+\tu32 data;\n+\tu8 bit;\n+\tint rmask_bits = RV1103_DRV_BITS_PER_PIN;\n+\n+\tret = rv1103b_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0, ret = 1; i < strength; i++)\n+\t\tret = (ret << 1) | 1;\n+\n+\tif (bank->bank_num == 2 && pin_num >= 12) {\n+\t\trmask_bits = 2;\n+\t\tret = strength;\n+\t}\n+\n+\t/* Enable the write to the equivalent lower bits */\n+\tdata = ((1 << rmask_bits) - 1) << (bit + 16);\n+\tdata |= (ret << bit);\n+\treturn regmap_write(regmap, reg, data);\n+}\n+\n+#define RV1103_PULL_BITS_PER_PIN\t\t2\n+#define RV1103_PULL_PINS_PER_REG\t\t8\n+#define RV1103_PULL_GPIO0_A_OFFSET\t\t0x40200\n+#define RV1103_PULL_GPIO0_B_OFFSET\t\t0x50204\n+#define RV1103_PULL_GPIO1_A01_OFFSET\t\t0x210\n+#define RV1103_PULL_GPIO1_A67_OFFSET\t\t0x10210\n+#define RV1103_PULL_GPIO2_OFFSET\t\t0x30220\n+#define RV1103_PULL_GPIO2_SARADC_OFFSET\t0x3080C\n+\n+static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t\tint pin_num, struct regmap **regmap,\n+\t\t\t\t\tint *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl_priv *priv = bank->priv;\n+\tint ret = 0;\n+\n+\t*regmap = priv->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103_PULL_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103_PULL_GPIO0_B_OFFSET - 0x4;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103_PULL_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103_PULL_GPIO1_A67_OFFSET;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103_PULL_GPIO1_A67_OFFSET;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103_PULL_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103_PULL_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 13;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tprintf(\"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103_PULL_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103_PULL_PINS_PER_REG;\n+\t*bit *= RV1103_PULL_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n+static int rv1103b_set_pull(struct rockchip_pin_bank *bank,\n+\t\t\t int pin_num, int pull)\n+{\n+\tstruct regmap *regmap;\n+\tint reg, ret;\n+\tu8 bit, type;\n+\tu32 data;\n+\n+\tif (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)\n+\t\treturn -EINVAL;\n+\n+\tret = rv1103b_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);\n+\tif (ret)\n+\t\treturn ret;\n+\ttype = bank->pull_type[pin_num / 8];\n+\n+\tif (bank->bank_num == 2 && pin_num >= 12)\n+\t\ttype = 1;\n+\n+\tret = rockchip_translate_pull_value(type, pull);\n+\tif (ret < 0) {\n+\t\tdebug(\"unsupported pull setting %d\\n\", pull);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Enable the write to the equivalent lower bits */\n+\tdata = ((1 << RV1103_PULL_BITS_PER_PIN) - 1) << (bit + 16);\n+\n+\tdata |= (ret << bit);\n+\tret = regmap_write(regmap, reg, data);\n+\n+\treturn ret;\n+}\n+\n+#define RV1103_SMT_BITS_PER_PIN\t\t1\n+#define RV1103_SMT_PINS_PER_REG\t\t8\n+#define RV1103_SMT_GPIO0_A_OFFSET\t\t0x40400\n+#define RV1103_SMT_GPIO0_B_OFFSET\t\t0x50404\n+#define RV1103_SMT_GPIO1_A01_OFFSET\t\t0x410\n+#define RV1103_SMT_GPIO1_A67_OFFSET\t\t0x10410\n+#define RV1103_SMT_GPIO2_OFFSET\t\t0x30420\n+#define RV1103_SMT_GPIO2_SARADC_OFFSET\t\t0x3080C\n+\n+static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,\n+\t\t\t\t\t int pin_num,\n+\t\t\t\t\t struct regmap **regmap,\n+\t\t\t\t\t int *reg, u8 *bit)\n+{\n+\tstruct rockchip_pinctrl_priv *priv = bank->priv;\n+\tint ret = 0;\n+\n+\t*regmap = priv->regmap_base;\n+\tswitch (bank->bank_num) {\n+\tcase 0:\n+\t\tif (pin_num < 7)\n+\t\t\t*reg = RV1103_SMT_GPIO0_A_OFFSET;\n+\t\telse if (pin_num > 7 && pin_num < 14)\n+\t\t\t*reg = RV1103_SMT_GPIO0_B_OFFSET - 0x4;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 1:\n+\t\tif (pin_num < 6)\n+\t\t\t*reg = RV1103_SMT_GPIO1_A01_OFFSET;\n+\t\telse if (pin_num >= 6 && pin_num < 23)\n+\t\t\t*reg = RV1103_SMT_GPIO1_A67_OFFSET;\n+\t\telse if (pin_num >= 24 && pin_num < 30)\n+\t\t\t*reg = RV1103_SMT_GPIO1_A67_OFFSET;\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tif (pin_num < 12) {\n+\t\t\t*reg = RV1103_SMT_GPIO2_OFFSET;\n+\t\t} else if (pin_num >= 16) {\n+\t\t\tret = -EINVAL;\n+\t\t} else {\n+\t\t\t*reg = RV1103_SMT_GPIO2_SARADC_OFFSET;\n+\t\t\t*bit = 8;\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (ret) {\n+\t\tprintf(\"unsupported bank_num %d pin_num %d\\n\", bank->bank_num, pin_num);\n+\t\treturn ret;\n+\t}\n+\n+\t*reg += ((pin_num / RV1103_SMT_PINS_PER_REG) * 4);\n+\t*bit = pin_num % RV1103_SMT_PINS_PER_REG;\n+\t*bit *= RV1103_SMT_BITS_PER_PIN;\n+\n+\treturn 0;\n+}\n+\n+static int rv1103b_set_schmitt(struct rockchip_pin_bank *bank,\n+\t\t\t int pin_num, int enable)\n+{\n+\tstruct regmap *regmap;\n+\tint reg, ret;\n+\tu32 data;\n+\tu8 bit;\n+\n+\tret = rv1103b_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* enable the write to the equivalent lower bits */\n+\tdata = ((1 << RV1103_SMT_BITS_PER_PIN) - 1) << (bit + 16);\n+\tdata |= (enable << bit);\n+\n+\tif (bank->bank_num == 2 && pin_num >= 12) {\n+\t\tdata = 0x3 << (bit + 16);\n+\t\tdata |= ((enable ? 0x3 : 0) << bit);\n+\t}\n+\treturn regmap_write(regmap, reg, data);\n+}\n+\n+static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {\n+\t{\n+\t\t.num = 1,\n+\t\t.pin = 6,\n+\t\t.reg = 0x10024,\n+\t\t.bit = 8,\n+\t\t.mask = 0xf\n+\t}, {\n+\t\t.num = 1,\n+\t\t.pin = 7,\n+\t\t.reg = 0x10024,\n+\t\t.bit = 12,\n+\t\t.mask = 0xf\n+\t},\n+};\n+\n+static struct rockchip_pin_bank rv1103b_pin_banks[] = {\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, \"gpio0\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x40000, 0x50008, 0x50010, 0x50018),\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, \"gpio1\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x20, 0x10028, 0x10030, 0x10038),\n+\tPIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, \"gpio2\",\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t IOMUX_WIDTH_4BIT,\n+\t\t\t\t 0x30040, 0x30048, 0x30050, 0x30058),\n+};\n+\n+static const struct rockchip_pin_ctrl rv1103b_pin_ctrl = {\n+\t.pin_banks\t\t= rv1103b_pin_banks,\n+\t.nr_banks\t\t= ARRAY_SIZE(rv1103b_pin_banks),\n+\t.iomux_recalced\t\t= rv1103b_mux_recalced_data,\n+\t.niomux_recalced\t= ARRAY_SIZE(rv1103b_mux_recalced_data),\n+\t.set_mux\t\t= rv1103b_set_mux,\n+\t.set_pull\t\t= rv1103b_set_pull,\n+\t.set_drive\t\t= rv1103b_set_drive,\n+\t.set_schmitt\t\t= rv1103b_set_schmitt,\n+};\n+\n+static const struct udevice_id rv1103b_pinctrl_ids[] = {\n+\t{\n+\t\t.compatible = \"rockchip,rv1103b-pinctrl\",\n+\t\t.data = (ulong)&rv1103b_pin_ctrl\n+\t},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(pinctrl_rv1103b) = {\n+\t.name\t\t= \"rockchip_rv1103b_pinctrl\",\n+\t.id\t\t= UCLASS_PINCTRL,\n+\t.of_match\t= rv1103b_pinctrl_ids,\n+\t.priv_auto\t= sizeof(struct rockchip_pinctrl_priv),\n+\t.ops\t\t= &rockchip_pinctrl_ops,\n+#if !CONFIG_IS_ENABLED(OF_PLATDATA)\n+\t.bind\t\t= dm_scan_fdt_dev,\n+#endif\n+\t.probe\t\t= rockchip_pinctrl_probe,\n+};\n", "prefixes": [ "v2", "2/7" ] }