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GET /api/patches/2194411/?format=api
{ "id": 2194411, "url": "http://patchwork.ozlabs.org/api/patches/2194411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-2-festevam@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208212624.3413494-2-festevam@gmail.com>", "list_archive_url": null, "date": "2026-02-08T21:26:18", "name": "[v2,1/7] ARM: dts: Add RV1103B Omega4 support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "d8a89f11f6f3407231b64f82d741b7c256932bbc", "submitter": { "id": 6978, "url": "http://patchwork.ozlabs.org/api/people/6978/?format=api", "name": "Fabio Estevam", "email": "festevam@gmail.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260208212624.3413494-2-festevam@gmail.com/mbox/", "series": [ { "id": 491441, "url": "http://patchwork.ozlabs.org/api/series/491441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=491441", "date": "2026-02-08T21:26:17", "name": "ARM: Add RV1103B Omega4 board support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/491441/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194411/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194411/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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00721157ae682-7952ab92c5fmr98307907b3.65.1770585995417;\n Sun, 08 Feb 2026 13:26:35 -0800 (PST)", "From": "Fabio Estevam <festevam@gmail.com>", "To": "kever.yang@rock-chips.com", "Cc": "trini@konsulko.com, jonas@kwiboo.se, u-boot@lists.denx.de,\n Fabio Estevam <festevam@nabladev.com>", "Subject": "[PATCH v2 1/7] ARM: dts: Add RV1103B Omega4 support", "Date": "Sun, 8 Feb 2026 18:26:18 -0300", "Message-Id": "<20260208212624.3413494-2-festevam@gmail.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208212624.3413494-1-festevam@gmail.com>", "References": "<20260208212624.3413494-1-festevam@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Fabio Estevam <festevam@nabladev.com>\n\nAdd the necessary devicetrees to support the RV1103B Omega4 board.\n\nThe RV1103B is a Rockchip SoC that is still not supported in Linux\nmainline.\n\nThe initial RV1103B support has already been submitted to Linux kernel\nand it is under review.\n\nOnce the Linux RV1103 devicetrees are upstreamed, the OF_UPSTREAM mechanism\ncan be enabled.\n\nSigned-off-by: Fabio Estevam <festevam@nabladev.com>\n---\nChanges since v1:\n- Used the devicetrees submitted to upstream Linux.\n\n arch/arm/dts/rv1103b-omega4-u-boot.dtsi | 10 +\n arch/arm/dts/rv1103b-omega4.dts | 105 +++\n arch/arm/dts/rv1103b-pinctrl.dtsi | 831 ++++++++++++++++++\n arch/arm/dts/rv1103b-u-boot.dtsi | 4 +\n arch/arm/dts/rv1103b.dtsi | 266 ++++++\n .../dt-bindings/clock/rockchip,rv1103b-cru.h | 220 +++++\n 6 files changed, 1436 insertions(+)\n create mode 100644 arch/arm/dts/rv1103b-omega4-u-boot.dtsi\n create mode 100644 arch/arm/dts/rv1103b-omega4.dts\n create mode 100644 arch/arm/dts/rv1103b-pinctrl.dtsi\n create mode 100644 arch/arm/dts/rv1103b-u-boot.dtsi\n create mode 100644 arch/arm/dts/rv1103b.dtsi\n create mode 100644 include/dt-bindings/clock/rockchip,rv1103b-cru.h", "diff": "diff --git a/arch/arm/dts/rv1103b-omega4-u-boot.dtsi b/arch/arm/dts/rv1103b-omega4-u-boot.dtsi\nnew file mode 100644\nindex 000000000000..c7616de1715c\n--- /dev/null\n+++ b/arch/arm/dts/rv1103b-omega4-u-boot.dtsi\n@@ -0,0 +1,10 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+// (C) Copyright 2024 Rockchip Electronics Co., Ltd\n+\n+#include \"rockchip-u-boot.dtsi\"\n+\n+/ {\n+\tchosen {\n+\t\tu-boot,spl-boot-order = &spi_nand;\n+\t};\n+};\ndiff --git a/arch/arm/dts/rv1103b-omega4.dts b/arch/arm/dts/rv1103b-omega4.dts\nnew file mode 100644\nindex 000000000000..3d58954d5e4a\n--- /dev/null\n+++ b/arch/arm/dts/rv1103b-omega4.dts\n@@ -0,0 +1,105 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.\n+ * Copyright (c) 2025 plan44.ch/luz\n+ * Copyright (c) 2025 Onion Corporation\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/leds/common.h>\n+#include \"rv1103b.dtsi\"\n+\n+/ {\n+\tmodel = \"Onion RV1103 Omega4 Board\";\n+\tcompatible = \"onion,rv1103b-omega4\", \"rockchip,rv1103b\";\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0\t{\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&led_pin>;\n+\t\t\tgpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tlabel = \"sys\";\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\t};\n+};\n+\n+&fspi0 {\n+\tstatus = \"okay\";\n+\n+\tspi_nand: flash@0 {\n+\t\tcompatible = \"spi-nand\";\n+\t\treg = <0>;\n+\t\tbootph-pre-ram;\n+\t\tbootph-some-ram;\n+\t\tspi-max-frequency = <75000000>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tspi-tx-bus-width = <1>;\n+\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"env\";\n+\t\t\t\treg = <0x00000000 0x00040000>;\n+\t\t\t};\n+\n+\t\t\tpartition@40000 {\n+\t\t\t\tlabel = \"idblock\";\n+\t\t\t\treg = <0x00040000 0x00100000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@140000 {\n+\t\t\t\tlabel = \"uboot\";\n+\t\t\t\treg = <0x00140000 0x00100000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@240000 {\n+\t\t\t\tlabel = \"boot\";\n+\t\t\t\treg = <0x00240000 0x00800000>;\n+\t\t\t};\n+\n+\t\t\tpartition@a40000 {\n+\t\t\t\tlabel = \"ubi\";\n+\t\t\t\treg = <0x00a40000 0x0f5c0000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0m0_xfer_pins>;\n+\tbootph-all;\n+\tstatus = \"okay\";\n+};\n+\n+&wdt {\n+\tstatus = \"okay\";\n+};\n+\n+&pinctrl {\n+\tleds {\n+\t\tled_pin: led-pin {\n+\t\t\trockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/rv1103b-pinctrl.dtsi b/arch/arm/dts/rv1103b-pinctrl.dtsi\nnew file mode 100644\nindex 000000000000..bc4d8fcdfaf7\n--- /dev/null\n+++ b/arch/arm/dts/rv1103b-pinctrl.dtsi\n@@ -0,0 +1,831 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.\n+ */\n+\n+#include <dt-bindings/pinctrl/rockchip.h>\n+#include <arm64/rockchip/rockchip-pinconf.dtsi>\n+\n+/*\n+ * This file is auto generated by pin2dts tool, please keep these code\n+ * by adding changes at end of this file.\n+ */\n+&pinctrl {\n+\tcam_clk0 {\n+\t\tcam_clk0_pins: cam-clk0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cam_clk0_out */\n+\t\t\t\t<1 RK_PB5 1 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tcam_clk1 {\n+\t\tcam_clk1_pins: cam-clk1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cam_clk1_out */\n+\t\t\t\t<1 RK_PB6 1 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tcam_spi {\n+\t\tcam_spi_bus4_pins: cam-spi-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cam_spi_d0 */\n+\t\t\t\t<0 RK_PB5 4 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* cam_spi_d1 */\n+\t\t\t\t<0 RK_PB2 4 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* cam_spi_d2 */\n+\t\t\t\t<0 RK_PB1 4 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* cam_spi_d3 */\n+\t\t\t\t<0 RK_PB0 4 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tcam_spi_clk_pins: cam-spi-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cam_spi_clk */\n+\t\t\t\t<0 RK_PB4 4 &pcfg_pull_none>;\n+\t\t};\n+\t\tcam_spi_cs0n_pins: cam-spi-cs0n-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cam_spi_cs0n */\n+\t\t\t\t<0 RK_PB3 4 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tclk {\n+\t\tclk_32k_pins: clk-32k-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* clk_32k */\n+\t\t\t\t<0 RK_PA0 2 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tclk_24m {\n+\t\tclk_24m_out_pins: clk-24m-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* clk_24m_out */\n+\t\t\t\t<0 RK_PA0 3 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tcpu {\n+\t\tcpu_pins: cpu-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* cpu_avs */\n+\t\t\t\t<0 RK_PA1 2 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\temmc {\n+\t\temmc_bus4_pins: emmc-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* emmc_d0 */\n+\t\t\t\t<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* emmc_d1 */\n+\t\t\t\t<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* emmc_d2 */\n+\t\t\t\t<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* emmc_d3 */\n+\t\t\t\t<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\temmc_clk_pins: emmc-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* emmc_clk */\n+\t\t\t\t<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\temmc_cmd_pins: emmc-cmd-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* emmc_cmd */\n+\t\t\t\t<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+\n+\temmc_testclk {\n+\t\temmc_testclk_clk_pins: emmc-testclk-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* emmc_testclk_out */\n+\t\t\t\t<1 RK_PA7 3 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+\n+\temmc_testdata {\n+\t\temmc_testdata_out_pins: emmc-testdata-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* emmc_testdata_out */\n+\t\t\t\t<1 RK_PB0 3 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\teth_led {\n+\t\teth_led_dpx_pins: eth-led-dpx-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* eth_led_dpx */\n+\t\t\t\t<2 RK_PA4 6 &pcfg_pull_none>;\n+\t\t};\n+\t\teth_led_link_pins: eth-led-link-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* eth_led_link */\n+\t\t\t\t<2 RK_PA6 6 &pcfg_pull_none>;\n+\t\t};\n+\t\teth_led_spd_pins: eth-led-spd-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* eth_led_spd */\n+\t\t\t\t<2 RK_PA7 6 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tflash_trig {\n+\t\tflash_trig_pins: flash-trig-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* flash_trig_out */\n+\t\t\t\t<2 RK_PB0 6 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tfspi {\n+\t\tfspi_bus4_pins: fspi-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* fspi_d0 */\n+\t\t\t\t<1 RK_PA1 2 &pcfg_pull_none>,\n+\t\t\t\t/* fspi_d1 */\n+\t\t\t\t<1 RK_PA2 2 &pcfg_pull_none>,\n+\t\t\t\t/* fspi_d2 */\n+\t\t\t\t<1 RK_PA3 2 &pcfg_pull_none>,\n+\t\t\t\t/* fspi_d3 */\n+\t\t\t\t<1 RK_PA0 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tfspi_cs0_pins: fspi-cs0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* fspi_cs0n */\n+\t\t\t\t<1 RK_PA5 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tfspi_clk_pins: fspi-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* fspi_clk */\n+\t\t\t\t<1 RK_PA4 2 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tfspi_testclk {\n+\t\tfspi_testclk_out_pins: fspi-testclk-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* fspi_testclk_out */\n+\t\t\t\t<1 RK_PA7 5 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tfspi_testdata {\n+\t\tfspi_testdata_out_pins: fspi-testdata-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* fspi_testdata_out */\n+\t\t\t\t<1 RK_PB0 5 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\ti2c0 {\n+\t\ti2c0m0_xfer_pins: i2c0m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c0_scl_m0 */\n+\t\t\t\t<0 RK_PA5 3 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c0_sda_m0 */\n+\t\t\t\t<0 RK_PA6 3 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c0m1_xfer_pins: i2c0m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c0_scl_m1 */\n+\t\t\t\t<1 RK_PB4 5 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c0_sda_m1 */\n+\t\t\t\t<1 RK_PB3 5 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c0m2_xfer_pins: i2c0m2-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c0_scl_m2 */\n+\t\t\t\t<1 RK_PB5 2 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c0_sda_m2 */\n+\t\t\t\t<1 RK_PB6 2 &pcfg_pull_none_smt>;\n+\t\t};\n+\t};\n+\n+\ti2c1 {\n+\t\ti2c1m0_xfer_pins: i2c1m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c1_scl_m0 */\n+\t\t\t\t<0 RK_PB0 1 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c1_sda_m0 */\n+\t\t\t\t<0 RK_PB1 1 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c1m1_xfer_pins: i2c1m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c1_scl_m1 */\n+\t\t\t\t<2 RK_PA4 4 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c1_sda_m1 */\n+\t\t\t\t<2 RK_PA5 4 &pcfg_pull_none_smt>;\n+\t\t};\n+\t};\n+\n+\ti2c2 {\n+\t\ti2c2m0_xfer_pins: i2c2m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c2_scl_m0 */\n+\t\t\t\t<0 RK_PB2 1 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c2_sda_m0 */\n+\t\t\t\t<0 RK_PB3 1 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c2m1_xfer_pins: i2c2m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c2_scl_m1 */\n+\t\t\t\t<2 RK_PA6 4 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c2_sda_m1 */\n+\t\t\t\t<2 RK_PA7 4 &pcfg_pull_none_smt>;\n+\t\t};\n+\t};\n+\n+\ti2c3 {\n+\t\ti2c3m0_xfer_pins: i2c3m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c3_scl_m0 */\n+\t\t\t\t<0 RK_PB4 1 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c3_sda_m0 */\n+\t\t\t\t<0 RK_PB5 1 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c3m1_xfer_pins: i2c3m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c3_scl_m1 */\n+\t\t\t\t<2 RK_PB3 4 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c3_sda_m1 */\n+\t\t\t\t<2 RK_PB2 4 &pcfg_pull_none_smt>;\n+\t\t};\n+\t};\n+\n+\ti2c4 {\n+\t\ti2c4m0_xfer_pins: i2c4m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c4_scl_m0 */\n+\t\t\t\t<2 RK_PB0 4 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c4_sda_m0 */\n+\t\t\t\t<2 RK_PB1 4 &pcfg_pull_none_smt>;\n+\t\t};\n+\t\ti2c4m1_xfer_pins: i2c4m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* i2c4_scl_m1 */\n+\t\t\t\t<1 RK_PB7 2 &pcfg_pull_none_smt>,\n+\t\t\t\t/* i2c4_sda_m1 */\n+\t\t\t\t<1 RK_PC0 2 &pcfg_pull_none_smt>;\n+\t\t};\n+\t};\n+\n+\tjtag {\n+\t\tjtagm0_pins: jtagm0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* jtag_tck_m0 */\n+\t\t\t\t<0 RK_PA5 5 &pcfg_pull_none>,\n+\t\t\t\t/* jtag_tms_m0 */\n+\t\t\t\t<0 RK_PA6 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tjtagm1_pins: jtagm1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* jtag_tck_m1 */\n+\t\t\t\t<0 RK_PB4 3 &pcfg_pull_none>,\n+\t\t\t\t/* jtag_tms_m1 */\n+\t\t\t\t<0 RK_PB5 3 &pcfg_pull_none>;\n+\t\t};\n+\t\tjtagm2_pins: jtagm2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* jtag_tck_m2 */\n+\t\t\t\t<1 RK_PB4 3 &pcfg_pull_none>,\n+\t\t\t\t/* jtag_tms_m2 */\n+\t\t\t\t<1 RK_PB3 3 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tpmu_debug_test {\n+\t\tpmu_debug_test_pins: pmu-debug-test-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pmu_debug_test_out */\n+\t\t\t\t<0 RK_PB1 5 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tprelight_trig {\n+\t\tprelight_trig_pins: prelight-trig-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* prelight_trig_out */\n+\t\t\t\t<2 RK_PB1 6 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tpsram_spi {\n+\t\tpsram_spi_bus4_pins: psram-spi-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* psram_spi_d0 */\n+\t\t\t\t<0 RK_PA2 4 &pcfg_pull_none>,\n+\t\t\t\t/* psram_spi_d1 */\n+\t\t\t\t<0 RK_PA1 4 &pcfg_pull_none>,\n+\t\t\t\t/* psram_spi_d2 */\n+\t\t\t\t<0 RK_PA5 4 &pcfg_pull_none>,\n+\t\t\t\t/* psram_spi_d3 */\n+\t\t\t\t<0 RK_PA6 4 &pcfg_pull_none>;\n+\t\t};\n+\t\tpsram_spi_clk_pins: psram-spi-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* psram_spi_clk */\n+\t\t\t\t<0 RK_PA0 4 &pcfg_pull_none>;\n+\t\t};\n+\t\tpsram_spi_cs0n_pins: psram-spi-cs0n-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* psram_spi_cs0n */\n+\t\t\t\t<0 RK_PA4 4 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tpwm0 {\n+\t\tpwm0m0_ch0_pins: pwm0m0-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m0_ch0 */\n+\t\t\t\t<0 RK_PA1 1 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m0_ch1_pins: pwm0m0-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m0_ch1 */\n+\t\t\t\t<0 RK_PA5 2 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m0_ch2_pins: pwm0m0-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m0_ch2 */\n+\t\t\t\t<0 RK_PA6 2 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m0_ch3_pins: pwm0m0-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m0_ch3 */\n+\t\t\t\t<0 RK_PA2 1 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m1_ch0_pins: pwm0m1-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m1_ch0 */\n+\t\t\t\t<2 RK_PA0 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m1_ch1_pins: pwm0m1-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m1_ch1 */\n+\t\t\t\t<2 RK_PA1 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m1_ch2_pins: pwm0m1-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m1_ch2 */\n+\t\t\t\t<2 RK_PA2 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m1_ch3_pins: pwm0m1-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m1_ch3 */\n+\t\t\t\t<2 RK_PB0 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m2_ch1_pins: pwm0m2-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m2_ch1 */\n+\t\t\t\t<1 RK_PB7 1 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm0m2_ch2_pins: pwm0m2-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm0m2_ch2 */\n+\t\t\t\t<1 RK_PC0 1 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t};\n+\n+\tpwm1 {\n+\t\tpwm1m0_ch0_pins: pwm1m0-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m0_ch0 */\n+\t\t\t\t<0 RK_PB0 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m0_ch1_pins: pwm1m0-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m0_ch1 */\n+\t\t\t\t<0 RK_PB1 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m0_ch2_pins: pwm1m0-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m0_ch2 */\n+\t\t\t\t<0 RK_PB2 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m0_ch3_pins: pwm1m0-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m0_ch3 */\n+\t\t\t\t<0 RK_PB3 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m1_ch0_pins: pwm1m1-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m1_ch0 */\n+\t\t\t\t<2 RK_PA3 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m1_ch1_pins: pwm1m1-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m1_ch1 */\n+\t\t\t\t<2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m1_ch2_pins: pwm1m1-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m1_ch2 */\n+\t\t\t\t<2 RK_PA5 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm1m1_ch3_pins: pwm1m1-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm1m1_ch3 */\n+\t\t\t\t<2 RK_PB1 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t};\n+\n+\tpwm2 {\n+\t\tpwm2m0_ch0_pins: pwm2m0-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m0_ch0 */\n+\t\t\t\t<1 RK_PB0 4 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m0_ch1_pins: pwm2m0-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m0_ch1 */\n+\t\t\t\t<1 RK_PA7 4 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m0_ch2_pins: pwm2m0-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m0_ch2 */\n+\t\t\t\t<1 RK_PB4 4 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m0_ch3_pins: pwm2m0-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m0_ch3 */\n+\t\t\t\t<1 RK_PB3 4 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m1_ch0_pins: pwm2m1-ch0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m1_ch0 */\n+\t\t\t\t<2 RK_PA6 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m1_ch1_pins: pwm2m1-ch1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m1_ch1 */\n+\t\t\t\t<2 RK_PA7 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m1_ch2_pins: pwm2m1-ch2-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m1_ch2 */\n+\t\t\t\t<2 RK_PB2 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t\tpwm2m1_ch3_pins: pwm2m1-ch3-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwm2m1_ch3 */\n+\t\t\t\t<2 RK_PB3 3 &pcfg_pull_none_drv_level_0>;\n+\t\t};\n+\t};\n+\n+\tpwr {\n+\t\tpwr_pins: pwr-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* pwr_ctrl0 */\n+\t\t\t\t<0 RK_PA3 1 &pcfg_pull_none>,\n+\t\t\t\t/* pwr_ctrl1 */\n+\t\t\t\t<0 RK_PA4 1 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\trtc_32k {\n+\t\trtc_32k_pins: rtc-32k-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* rtc_32k_out */\n+\t\t\t\t<0 RK_PA0 1 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tsai {\n+\t\tsai_pins: sai-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sai_lrck */\n+\t\t\t\t<2 RK_PB1 5 &pcfg_pull_none>,\n+\t\t\t\t/* sai_mclk */\n+\t\t\t\t<2 RK_PB0 5 &pcfg_pull_none>,\n+\t\t\t\t/* sai_sclk */\n+\t\t\t\t<2 RK_PA7 5 &pcfg_pull_none>,\n+\t\t\t\t/* sai_sdi */\n+\t\t\t\t<2 RK_PA6 5 &pcfg_pull_none>,\n+\t\t\t\t/* sai_sdo */\n+\t\t\t\t<2 RK_PB2 5 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tsdmmc0 {\n+\t\tsdmmc0_bus4_pins: sdmmc0-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_d0 */\n+\t\t\t\t<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc0_d1 */\n+\t\t\t\t<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc0_d2 */\n+\t\t\t\t<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc0_d3 */\n+\t\t\t\t<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc0_clk_pins: sdmmc0-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_clk */\n+\t\t\t\t<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc0_cmd_pins: sdmmc0-cmd-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_cmd */\n+\t\t\t\t<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc0_det_pins: sdmmc0-det-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_det */\n+\t\t\t\t<1 RK_PA6 1 &pcfg_pull_up>;\n+\t\t};\n+\t};\n+\n+\tsdmmc1 {\n+\t\tsdmmc1_bus4_pins: sdmmc1-bus4-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_d0 */\n+\t\t\t\t<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc1_d1 */\n+\t\t\t\t<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc1_d2 */\n+\t\t\t\t<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,\n+\t\t\t\t/* sdmmc1_d3 */\n+\t\t\t\t<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc1_clk_pins: sdmmc1-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_clk */\n+\t\t\t\t<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc1_cmd_pins: sdmmc1-cmd-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_cmd */\n+\t\t\t\t<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+\n+\tsdmmc0_testclk {\n+\t\tsdmmc0_testclk_clk_pins: sdmmc0-testclk-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_testclk_out */\n+\t\t\t\t<1 RK_PA0 3 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+\n+\tsdmmc0_testdata {\n+\t\tsdmmc0_testdata_out_pins: sdmmc0-testdata-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_testdata_out */\n+\t\t\t\t<1 RK_PA3 3 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tsdmmc1_testclk {\n+\t\tsdmmc1_testclk_clk_pins: sdmmc1-testclk-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_testclk_out */\n+\t\t\t\t<2 RK_PA6 7 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+\n+\tsdmmc1_testdata {\n+\t\tsdmmc1_testdata_out_pins: sdmmc1-testdata-out-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_testdata_out */\n+\t\t\t\t<2 RK_PA7 7 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tspi0 {\n+\t\tspi0m0_clk_pins: spi0m0-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_clk_m0 */\n+\t\t\t\t<2 RK_PB0 2 &pcfg_pull_none>,\n+\t\t\t\t/* spi0_miso_m0 */\n+\t\t\t\t<2 RK_PB3 2 &pcfg_pull_none>,\n+\t\t\t\t/* spi0_mosi_m0 */\n+\t\t\t\t<2 RK_PB1 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tspi0m0_cs0_pins: spi0m0-cs0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_cs0n_m0 */\n+\t\t\t\t<2 RK_PB2 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tspi0m0_cs1_pins: spi0m0-cs1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_cs1n_m0 */\n+\t\t\t\t<2 RK_PA7 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tspi0m1_clk_pins: spi0m1-clk-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_clk_m1 */\n+\t\t\t\t<2 RK_PA2 5 &pcfg_pull_none>,\n+\t\t\t\t/* spi0_miso_m1 */\n+\t\t\t\t<2 RK_PA4 5 &pcfg_pull_none>,\n+\t\t\t\t/* spi0_mosi_m1 */\n+\t\t\t\t<2 RK_PA1 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tspi0m1_cs0_pins: spi0m1-cs0-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_cs0n_m1 */\n+\t\t\t\t<2 RK_PA3 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tspi0m1_cs1_pins: spi0m1-cs1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* spi0_cs1n_m1 */\n+\t\t\t\t<2 RK_PA0 5 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tuart0 {\n+\t\tuart0m0_xfer_pins: uart0m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart0_rx_m0 */\n+\t\t\t\t<0 RK_PA6 1 &pcfg_pull_up>,\n+\t\t\t\t/* uart0_tx_m0 */\n+\t\t\t\t<0 RK_PA5 1 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart0m1_xfer_pins: uart0m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart0_rx_m1 */\n+\t\t\t\t<0 RK_PB5 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart0_tx_m1 */\n+\t\t\t\t<0 RK_PB4 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart0m2_xfer_pins: uart0m2-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart0_rx_m2 */\n+\t\t\t\t<1 RK_PB3 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart0_tx_m2 */\n+\t\t\t\t<1 RK_PB4 2 &pcfg_pull_up>;\n+\t\t};\n+\t};\n+\n+\tuart1 {\n+\t\tuart1m0_xfer_pins: uart1m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1_rx_m0 */\n+\t\t\t\t<0 RK_PB2 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart1_tx_m0 */\n+\t\t\t\t<0 RK_PB3 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart1m0_ctsn_pins: uart1m0-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m0_ctsn */\n+\t\t\t\t<0 RK_PB5 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m0_rtsn_pins: uart1m0-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m0_rtsn */\n+\t\t\t\t<0 RK_PB4 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m1_xfer_pins: uart1m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1_rx_m1 */\n+\t\t\t\t<1 RK_PA7 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart1_tx_m1 */\n+\t\t\t\t<1 RK_PB0 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart1m1_ctsn_pins: uart1m1-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m1_ctsn */\n+\t\t\t\t<1 RK_PB2 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m1_rtsn_pins: uart1m1-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m1_rtsn */\n+\t\t\t\t<1 RK_PB1 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m2_xfer_pins: uart1m2-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1_rx_m2 */\n+\t\t\t\t<2 RK_PA7 1 &pcfg_pull_up>,\n+\t\t\t\t/* uart1_tx_m2 */\n+\t\t\t\t<2 RK_PA6 1 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart1m2_ctsn_pins: uart1m2-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m2_ctsn */\n+\t\t\t\t<2 RK_PA5 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m2_rtsn_pins: uart1m2-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m2_rtsn */\n+\t\t\t\t<2 RK_PA4 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m3_xfer_pins: uart1m3-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1_rx_m3 */\n+\t\t\t\t<2 RK_PA3 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart1_tx_m3 */\n+\t\t\t\t<2 RK_PA2 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart1m3_ctsn_pins: uart1m3-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m3_ctsn */\n+\t\t\t\t<2 RK_PA1 2 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart1m3_rtsn_pins: uart1m3-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart1m3_rtsn */\n+\t\t\t\t<2 RK_PA0 2 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\tuart2 {\n+\t\tuart2m0_xfer_pins: uart2m0-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2_rx_m0 */\n+\t\t\t\t<0 RK_PB1 2 &pcfg_pull_up>,\n+\t\t\t\t/* uart2_tx_m0 */\n+\t\t\t\t<0 RK_PB0 2 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart2m0_ctsn_pins: uart2m0-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m0_ctsn */\n+\t\t\t\t<0 RK_PB3 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart2m0_rtsn_pins: uart2m0-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m0_rtsn */\n+\t\t\t\t<0 RK_PB2 5 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart2m1_xfer_pins: uart2m1-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2_rx_m1 */\n+\t\t\t\t<2 RK_PB1 1 &pcfg_pull_up>,\n+\t\t\t\t/* uart2_tx_m1 */\n+\t\t\t\t<2 RK_PB0 1 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart2m1_ctsn_pins: uart2m1-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m1_ctsn */\n+\t\t\t\t<2 RK_PB3 1 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart2m1_rtsn_pins: uart2m1-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m1_rtsn */\n+\t\t\t\t<2 RK_PB2 1 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart2m2_xfer_pins: uart2m2-xfer-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2_rx_m2 */\n+\t\t\t\t<1 RK_PB6 3 &pcfg_pull_up>,\n+\t\t\t\t/* uart2_tx_m2 */\n+\t\t\t\t<1 RK_PB5 3 &pcfg_pull_up>;\n+\t\t};\n+\t\tuart2m2_ctsn_pins: uart2m2-ctsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m2_ctsn */\n+\t\t\t\t<1 RK_PC0 3 &pcfg_pull_none>;\n+\t\t};\n+\t\tuart2m2_rtsn_pins: uart2m2-rtsn-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* uart2m2_rtsn */\n+\t\t\t\t<1 RK_PB7 3 &pcfg_pull_none>;\n+\t\t};\n+\t};\n+};\n+\n+&pinctrl {\n+\tsdmmc0 {\n+\t\tsdmmc0_clk_idle_pins: sdmmc0-clk-idle-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_clk */\n+\t\t\t\t<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;\n+\t\t};\n+\t\tsdmmc0_cmd_idle_pins: sdmmc0-cmd-idle-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_cmd */\n+\t\t\t\t<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;\n+\t\t};\n+\t\tsdmmc0_bus1_pins: sdmmc0-bus1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_d0 */\n+\t\t\t\t<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t\tsdmmc0_bus1_idle_pins: sdmmc0-bus1-idle-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_d0 */\n+\t\t\t\t<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;\n+\t\t};\n+\t\tsdmmc0_bus4_idle_pins: sdmmc0-bus4-idle-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc0_d0 */\n+\t\t\t\t<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>,\n+\t\t\t\t/* sdmmc0_d1 */\n+\t\t\t\t<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,\n+\t\t\t\t/* sdmmc0_d2 */\n+\t\t\t\t<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>,\n+\t\t\t\t/* sdmmc0_d3 */\n+\t\t\t\t<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;\n+\t\t};\n+\t};\n+\n+\tsdmmc1 {\n+\t\tsdmmc1_bus1_pins: sdmmc1-bus1-pins {\n+\t\t\trockchip,pins =\n+\t\t\t\t/* sdmmc1_d0 */\n+\t\t\t\t<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/rv1103b-u-boot.dtsi b/arch/arm/dts/rv1103b-u-boot.dtsi\nnew file mode 100644\nindex 000000000000..3b77dd31152f\n--- /dev/null\n+++ b/arch/arm/dts/rv1103b-u-boot.dtsi\n@@ -0,0 +1,4 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+// (C) Copyright 2024 Rockchip Electronics Co., Ltd\n+\n+#include \"rockchip-u-boot.dtsi\"\ndiff --git a/arch/arm/dts/rv1103b.dtsi b/arch/arm/dts/rv1103b.dtsi\nnew file mode 100644\nindex 000000000000..5c850aa56de7\n--- /dev/null\n+++ b/arch/arm/dts/rv1103b.dtsi\n@@ -0,0 +1,266 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.\n+ */\n+\n+#include <dt-bindings/clock/rockchip,rv1103b-cru.h>\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/pinctrl/rockchip.h>\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\n+\tcompatible = \"rockchip,rv1103b\";\n+\n+\tinterrupt-parent = <&gic>;\n+\n+\tarm-pmu {\n+\t\tcompatible = \"arm,cortex-a7-pmu\";\n+\t\tinterrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-affinity = <&cpu0>;\n+\t};\n+\n+\txin32k: oscillator-32k {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <32768>;\n+\t\tclock-output-names = \"xin32k\";\n+\t\t#clock-cells = <0>;\n+\t};\n+\n+\txin24m: oscillator-24m {\n+\t\tcompatible = \"fixed-clock\";\n+\t\tclock-frequency = <24000000>;\n+\t\tclock-output-names = \"xin24m\";\n+\t\t#clock-cells = <0>;\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x0>;\n+\t\t\tclocks = <&cru ARMCLK>;\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv7-timer\";\n+\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,\n+\t\t\t <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t\tclock-frequency = <24000000>;\n+\t};\n+\n+\tcru: clock-controller@20000000 {\n+\t\tcompatible = \"rockchip,rv1103b-cru\";\n+\t\treg = <0x20000000 0x81000>;\n+\t\t#clock-cells = <1>;\n+\t\t#reset-cells = <1>;\n+\t\tbootph-all;\n+\t\tassigned-clocks = <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>;\n+\t\tassigned-clock-rates = <1188000000>, <100000000>;\n+\t};\n+\n+\t/*\n+\t * Merge all GRF, each independent GRF offset is shown as bellow:\n+\t * VEPU_GRF:\t\t0x20100000\n+\t * NPU_GRF:\t\t0x20110000\n+\t * VI_GRF:\t\t0x20120000\n+\t * CPU_GRF:\t\t0x20130000\n+\t * DDR_GRF:\t\t0x20140000\n+\t * SYS_GRF:\t\t0x20150000\n+\t * PMU_GRF:\t\t0x20160000\n+\t */\n+\tgrf: syscon@20100000 {\n+\t\tcompatible = \"rockchip,rv1103b-grf\", \"syscon\", \"simple-mfd\";\n+\t\treg = <0x20100000 0x61000>;\n+\n+\t\treboot_mode: reboot-mode {\n+\t\t\tcompatible = \"syscon-reboot-mode\";\n+\t\t\toffset = <0x60200>;\n+\t\t};\n+\t};\n+\n+\tioc: syscon@20170000 {\n+\t\tcompatible = \"rockchip,rv1103b-ioc\", \"syscon\";\n+\t\treg = <0x20170000 0x60000>;\n+\t};\n+\n+\tgic: interrupt-controller@20411000 {\n+\t\tcompatible = \"arm,gic-400\";\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <3>;\n+\t\t#address-cells = <0>;\n+\n+\t\treg = <0x20411000 0x1000>,\n+\t\t <0x20412000 0x2000>,\n+\t\t <0x20414000 0x2000>,\n+\t\t <0x20416000 0x2000>;\n+\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t};\n+\n+\tuart0: serial@20540000 {\n+\t\tcompatible = \"rockchip,rv1103b-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20540000 0x100>;\n+\t\tinterrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart0m0_xfer_pins>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tsdmmc1: mmc@20650000 {\n+\t\tcompatible = \"rockchip,rv1103b-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n+\t\treg = <0x20650000 0x4000>;\n+\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;\n+\t\tclock-names = \"biu\", \"ciu\";\n+\t\tfifo-depth = <0x100>;\n+\t\tmax-frequency = <150000000>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tuart1: serial@20870000 {\n+\t\tcompatible = \"rockchip,rv1103b-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20870000 0x100>;\n+\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart1m0_xfer_pins>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tuart2: serial@20880000 {\n+\t\tcompatible = \"rockchip,rv1103b-uart\", \"snps,dw-apb-uart\";\n+\t\treg = <0x20880000 0x100>;\n+\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\t\tclock-frequency = <24000000>;\n+\t\tclocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;\n+\t\tclock-names = \"baudclk\", \"apb_pclk\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&uart2m0_xfer_pins>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\twdt: watchdog@208d0000 {\n+\t\tcompatible = \"snps,dw-wdt\";\n+\t\treg = <0x208d0000 0x100>;\n+\t\tclocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;\n+\t\tclock-names = \"tclk\", \"pclk\";\n+\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tsdmmc0: mmc@20d20000 {\n+\t\tcompatible = \"rockchip,rv1103b-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n+\t\treg = <0x20d20000 0x4000>;\n+\t\tinterrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;\n+\t\tclock-names = \"biu\", \"ciu\";\n+\t\tfifo-depth = <0x100>;\n+\t\tmax-frequency = <150000000>;\n+\t\tpinctrl-names = \"normal\", \"idle\";\n+\t\tpinctrl-0 = <&sdmmc0_det_pins\n+\t\t\t &sdmmc0_clk_pins\n+\t\t\t &sdmmc0_cmd_pins\n+\t\t\t &sdmmc0_bus4_pins>;\n+\t\tpinctrl-1 = <&sdmmc0_det_pins\n+\t\t\t &sdmmc0_clk_idle_pins\n+\t\t\t &sdmmc0_cmd_idle_pins\n+\t\t\t &sdmmc0_bus4_idle_pins>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\temmc: mmc@20d30000 {\n+\t\tcompatible = \"rockchip,rv1103b-dw-mshc\", \"rockchip,rk3288-dw-mshc\";\n+\t\treg = <0x20d30000 0x4000>;\n+\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;\n+\t\tclock-names = \"biu\", \"ciu\";\n+\t\tfifo-depth = <0x100>;\n+\t\tmax-frequency = <150000000>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tfspi0: spi@20d40000 {\n+\t\tcompatible = \"rockchip,sfc\";\n+\t\treg = <0x20d40000 0x4000>;\n+\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;\n+\t\tclock-names = \"clk_sfc\", \"hclk_sfc\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tsystem_sram: sram@210f6000 {\n+\t\tcompatible = \"mmio-sram\";\n+\t\treg = <0x210f6000 0x8000>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0 0x210f6000 0x8000>;\n+\t};\n+\n+\tpinctrl: pinctrl {\n+\t\tcompatible = \"rockchip,rv1103b-pinctrl\";\n+\t\trockchip,grf = <&ioc>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tgpio0: gpio@20520000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20520000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&pinctrl 0 0 32>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgpio1: gpio@20d80000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20d80000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&pinctrl 0 32 32>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgpio2: gpio@20840000 {\n+\t\t\tcompatible = \"rockchip,gpio-bank\";\n+\t\t\treg = <0x20840000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&pinctrl 0 64 32>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\t};\n+};\n+\n+#include \"rv1103b-pinctrl.dtsi\"\ndiff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h\nnew file mode 100644\nindex 000000000000..35afdee7e961\n--- /dev/null\n+++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h\n@@ -0,0 +1,220 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */\n+/*\n+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.\n+ * Author: Elaine Zhang <zhangqing@rock-chips.com>\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H\n+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H\n+\n+#define PLL_GPLL\t\t0\n+#define ARMCLK\t\t\t1\n+#define PLL_DPLL\t\t2\n+#define XIN_OSC0_HALF\t\t3\n+#define CLK_GPLL_DIV24\t\t4\n+#define CLK_GPLL_DIV12\t\t5\n+#define CLK_GPLL_DIV6\t\t6\n+#define CLK_GPLL_DIV4\t\t7\n+#define CLK_GPLL_DIV3\t\t8\n+#define CLK_GPLL_DIV2P5\t\t9\n+#define CLK_GPLL_DIV2\t\t10\n+#define CLK_UART0_SRC\t\t11\n+#define CLK_UART1_SRC\t\t12\n+#define CLK_UART2_SRC\t\t13\n+#define CLK_UART0_FRAC\t\t14\n+#define CLK_UART1_FRAC\t\t15\n+#define CLK_UART2_FRAC\t\t16\n+#define CLK_SAI_SRC\t\t17\n+#define CLK_SAI_FRAC\t\t18\n+#define LSCLK_NPU_SRC\t\t19\n+#define CLK_NPU_SRC\t\t20\n+#define ACLK_VEPU_SRC\t\t21\n+#define CLK_VEPU_SRC\t\t22\n+#define ACLK_VI_SRC\t\t23\n+#define CLK_ISP_SRC\t\t24\n+#define DCLK_VICAP\t\t25\n+#define CCLK_EMMC\t\t26\n+#define CCLK_SDMMC0\t\t27\n+#define SCLK_SFC_2X\t\t28\n+#define LSCLK_PERI_SRC\t\t29\n+#define ACLK_PERI_SRC\t\t30\n+#define HCLK_HPMCU\t\t31\n+#define SCLK_UART0\t\t32\n+#define SCLK_UART1\t\t33\n+#define SCLK_UART2\t\t34\n+#define CLK_I2C_PMU\t\t35\n+#define CLK_I2C_PERI\t\t36\n+#define CLK_SPI0\t\t37\n+#define CLK_PWM0_SRC\t\t38\n+#define CLK_PWM1\t\t39\n+#define CLK_PWM2\t\t40\n+#define DCLK_DECOM_SRC\t\t41\n+#define CCLK_SDMMC1\t\t42\n+#define CLK_CORE_CRYPTO\t\t43\n+#define CLK_PKA_CRYPTO\t\t44\n+#define CLK_CORE_RGA\t\t45\n+#define MCLK_SAI_SRC\t\t46\n+#define CLK_FREQ_PWM0_SRC\t47\n+#define CLK_COUNTER_PWM0_SRC\t48\n+#define PCLK_TOP_ROOT\t\t49\n+#define CLK_REF_MIPI0\t\t50\n+#define CLK_MIPI0_OUT2IO\t51\n+#define CLK_REF_MIPI1\t\t52\n+#define CLK_MIPI1_OUT2IO\t53\n+#define MCLK_SAI_OUT2IO\t\t54\n+#define ACLK_NPU_ROOT\t\t55\n+#define HCLK_RKNN\t\t56\n+#define ACLK_RKNN\t\t57\n+#define LSCLK_VEPU_ROOT\t\t58\n+#define HCLK_VEPU\t\t59\n+#define ACLK_VEPU\t\t60\n+#define CLK_CORE_VEPU\t\t61\n+#define PCLK_IOC_VCCIO3\t\t62\n+#define PCLK_ACODEC\t\t63\n+#define PCLK_USBPHY\t\t64\n+#define LSCLK_VI_100M\t\t65\n+#define LSCLK_VI_ROOT\t\t66\n+#define HCLK_ISP\t\t67\n+#define ACLK_ISP\t\t68\n+#define CLK_CORE_ISP\t\t69\n+#define ACLK_VICAP\t\t70\n+#define HCLK_VICAP\t\t71\n+#define ISP0CLK_VICAP\t\t72\n+#define PCLK_CSI2HOST0\t\t73\n+#define PCLK_CSI2HOST1\t\t74\n+#define HCLK_EMMC\t\t75\n+#define HCLK_SFC\t\t76\n+#define HCLK_SFC_XIP\t\t77\n+#define HCLK_SDMMC0\t\t78\n+#define PCLK_CSIPHY\t\t79\n+#define PCLK_GPIO1\t\t80\n+#define DBCLK_GPIO1\t\t81\n+#define PCLK_IOC_VCCIO47\t82\n+#define LSCLK_DDR_ROOT\t\t83\n+#define CLK_TIMER_DDRMON\t84\n+#define LSCLK_PMU_ROOT\t\t85\n+#define PCLK_PMU\t\t86\n+#define XIN_RC_DIV\t\t87\n+#define CLK_32K\t\t\t88\n+#define PCLK_PMU_GPIO0\t\t89\n+#define DBCLK_PMU_GPIO0\t\t90\n+#define CLK_DDR_FAIL_SAFE\t91\n+#define PCLK_PMU_HP_TIMER\t92\n+#define CLK_PMU_32K_HP_TIMER\t93\n+#define PCLK_PWM0\t\t94\n+#define CLK_PWM0\t\t95\n+#define CLK_OSC_PWM0\t\t96\n+#define CLK_RC_PWM0\t\t97\n+#define CLK_FREQ_PWM0\t\t98\n+#define CLK_COUNTER_PWM0\t99\n+#define PCLK_I2C0\t\t100\n+#define CLK_I2C0\t\t101\n+#define PCLK_UART0\t\t102\n+#define PCLK_IOC_PMUIO0\t\t103\n+#define CLK_REFOUT\t\t104\n+#define CLK_PREROLL\t\t105\n+#define CLK_PREROLL_32K\t\t106\n+#define CLK_LPMCU_PMU\t\t107\n+#define PCLK_SPI2AHB\t\t108\n+#define HCLK_SPI2AHB\t\t109\n+#define SCLK_SPI2AHB\t\t110\n+#define PCLK_WDT_LPMCU\t\t111\n+#define TCLK_WDT_LPMCU\t\t112\n+#define HCLK_SFC_PMU1\t\t113\n+#define HCLK_SFC_XIP_PMU1\t114\n+#define SCLK_SFC_2X_PMU1\t115\n+#define CLK_LPMCU\t\t116\n+#define CLK_LPMCU_RTC\t\t117\n+#define PCLK_LPMCU_MAILBOX\t118\n+#define PCLK_IOC_PMUIO1\t\t119\n+#define PCLK_CRU_PMU1\t\t120\n+#define PCLK_PERI_ROOT\t\t121\n+#define PCLK_RTC_ROOT\t\t122\n+#define CLK_TIMER_ROOT\t\t123\n+#define PCLK_TIMER\t\t124\n+#define CLK_TIMER0\t\t125\n+#define CLK_TIMER1\t\t126\n+#define CLK_TIMER2\t\t127\n+#define CLK_TIMER3\t\t128\n+#define CLK_TIMER4\t\t129\n+#define CLK_TIMER5\t\t130\n+#define PCLK_STIMER\t\t131\n+#define CLK_STIMER0\t\t132\n+#define CLK_STIMER1\t\t133\n+#define PCLK_WDT_NS\t\t134\n+#define TCLK_WDT_NS\t\t135\n+#define PCLK_WDT_S\t\t136\n+#define TCLK_WDT_S\t\t137\n+#define PCLK_WDT_HPMCU\t\t138\n+#define TCLK_WDT_HPMCU\t\t139\n+#define PCLK_I2C1\t\t140\n+#define CLK_I2C1\t\t141\n+#define PCLK_I2C2\t\t142\n+#define CLK_I2C2\t\t143\n+#define PCLK_I2C3\t\t144\n+#define CLK_I2C3\t\t145\n+#define PCLK_I2C4\t\t146\n+#define CLK_I2C4\t\t147\n+#define PCLK_SPI0\t\t148\n+#define PCLK_PWM1\t\t149\n+#define CLK_OSC_PWM1\t\t150\n+#define PCLK_PWM2\t\t151\n+#define CLK_OSC_PWM2\t\t152\n+#define PCLK_UART2\t\t153\n+#define PCLK_UART1\t\t154\n+#define ACLK_RKDMA\t\t155\n+#define PCLK_TSADC\t\t156\n+#define CLK_TSADC\t\t157\n+#define CLK_TSADC_TSEN\t\t158\n+#define PCLK_SARADC\t\t159\n+#define CLK_SARADC\t\t160\n+#define PCLK_GPIO2\t\t161\n+#define DBCLK_GPIO2\t\t162\n+#define PCLK_IOC_VCCIO6\t\t163\n+#define ACLK_USBOTG\t\t164\n+#define CLK_REF_USBOTG\t\t165\n+#define HCLK_SDMMC1\t\t166\n+#define HCLK_SAI\t\t167\n+#define MCLK_SAI\t\t168\n+#define ACLK_CRYPTO\t\t169\n+#define HCLK_CRYPTO\t\t170\n+#define HCLK_RK_RNG_NS\t\t171\n+#define HCLK_RK_RNG_S\t\t172\n+#define PCLK_OTPC_NS\t\t173\n+#define CLK_OTPC_ROOT_NS\t174\n+#define CLK_SBPI_OTPC_NS\t175\n+#define CLK_USER_OTPC_NS\t176\n+#define PCLK_OTPC_S\t\t177\n+#define CLK_OTPC_ROOT_S\t\t178\n+#define CLK_SBPI_OTPC_S\t\t179\n+#define CLK_USER_OTPC_S\t\t180\n+#define CLK_OTPC_ARB\t\t181\n+#define PCLK_OTP_MASK\t\t182\n+#define HCLK_RGA\t\t183\n+#define ACLK_RGA\t\t184\n+#define ACLK_MAC\t\t185\n+#define PCLK_MAC\t\t186\n+#define CLK_MACPHY\t\t187\n+#define ACLK_SPINLOCK\t\t188\n+#define HCLK_CACHE\t\t189\n+#define PCLK_HPMCU_MAILBOX\t190\n+#define PCLK_HPMCU_INTMUX\t191\n+#define CLK_HPMCU\t\t192\n+#define CLK_HPMCU_RTC\t\t193\n+#define DCLK_DECOM\t\t194\n+#define ACLK_DECOM\t\t195\n+#define PCLK_DECOM\t\t196\n+#define ACLK_SYS_SRAM\t\t197\n+#define PCLK_DMA2DDR\t\t198\n+#define ACLK_DMA2DDR\t\t199\n+#define PCLK_DCF\t\t200\n+#define ACLK_DCF\t\t201\n+#define MCLK_ACODEC_TX\t\t202\n+#define SCLK_UART0_SRC\t\t203\n+#define SCLK_UART1_SRC\t\t204\n+#define SCLK_UART2_SRC\t\t205\n+#define XIN_RC_SRC\t\t206\n+#define CLK_UTMI_USBOTG\t\t207\n+#define CLK_REF_USBPHY\t\t208\n+\n+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H\n", "prefixes": [ "v2", "1/7" ] }