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GET /api/patches/2194374/?format=api
{ "id": 2194374, "url": "http://patchwork.ozlabs.org/api/patches/2194374/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-9-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-9-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:35", "name": "[V5,8/9] PCI: tegra194: Add core monitor clock support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "338ee9400ed7577e2a210da732f009fa29b4f45f", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-9-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491430, "url": "http://patchwork.ozlabs.org/api/series/491430/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491430", "date": "2026-02-08T18:09:27", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491430/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194374/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194374/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11877-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,8/9] PCI: tegra194: Add core monitor clock support", "Date": "Sun, 8 Feb 2026 23:39:35 +0530", "Message-ID": "<20260208180936.2026329-9-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t8XeVkygjbYWJ4PZaHcZu7rrGr26pAG076cCXeXivoujZNYCf1EgeFcHTdG4NxuWeFbY64ClLWlPLvu/klpEM3jelgITWEY5WEqDKrPhCZCzQccZFS33X+w+1w7/u04GAOY+/DBatvuAHyuw0cbdlXWTNJXt9fq3Z5yBwU2Lni0r7UlhBvi5gVMpUjbKhahL6ftjHKiL48z1coAoaq4d40qpzC2nDZl+WY5TvJCnEaUoBFEZBUk91UtvAyjGzUTORMrw7E3ExsnuLofnI0tc8eIje+Uyeq2te9BvjMp+21zchxYBXbb72+5MEgquCISFwipbAZxKU4c2zl13T4qhcSzMDuIXgH+/JsN7zD8D17kN+rb2kbuVgciOpmjH7yI3/CmMOa4BiMT2GoJWH9XSCTDxW3kBbcX88f5Eq96eu45MmXy6BcO45AeywwCcGcFfE", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:10:57.6302\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fa0ac583-d16e-488c-8b0a-08de673d688a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E7.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB6213" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nTegra supports PCIe core clock monitoring for any rate changes that may be\nhappening because of the link speed changes. This is useful in tracking\nany changes in the core clock that are not initiated by the software. This\npatch adds support to parse the monitor clock info from device-tree and\nenable it if present.\n\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 96581fcd8693..82e9ef172de1 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -253,6 +253,7 @@ struct tegra_pcie_dw {\n \tstruct resource *atu_dma_res;\n \tvoid __iomem *appl_base;\n \tstruct clk *core_clk;\n+\tstruct clk *core_clk_m;\n \tstruct reset_control *core_apb_rst;\n \tstruct reset_control *core_rst;\n \tstruct dw_pcie pci;\n@@ -949,6 +950,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)\n \t}\n \n \tclk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);\n+\tif (clk_prepare_enable(pcie->core_clk_m))\n+\t\tdev_err(pci->dev, \"Failed to enable core monitor clock\\n\");\n \n \treturn 0;\n }\n@@ -1021,6 +1024,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)\n \t\tval &= ~PCI_DLF_EXCHANGE_ENABLE;\n \t\tdw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);\n \n+\t\t/*\n+\t\t * core_clk_m is enabled as part of host_init callback in\n+\t\t * dw_pcie_host_init(). Disable the clock since below\n+\t\t * tegra_pcie_dw_host_init() will enable it again.\n+\t\t */\n+\t\tclk_disable_unprepare(pcie->core_clk_m);\n \t\ttegra_pcie_dw_host_init(pp);\n \t\tdw_pcie_setup_rc(pp);\n \n@@ -1613,6 +1622,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \n static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)\n {\n+\tclk_disable_unprepare(pcie->core_clk_m);\n \tdw_pcie_host_deinit(&pcie->pci.pp);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n@@ -2160,6 +2170,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)\n \t\treturn PTR_ERR(pcie->core_clk);\n \t}\n \n+\tpcie->core_clk_m = devm_clk_get_optional(dev, \"core_m\");\n+\tif (IS_ERR(pcie->core_clk_m)) {\n+\t\tdev_err(dev, \"Failed to get monitor clock: %ld\\n\",\n+\t\t\tPTR_ERR(pcie->core_clk_m));\n+\t\treturn PTR_ERR(pcie->core_clk_m);\n+\t}\n+\n \tpcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n \t\t\t\t\t\t \"appl\");\n \tif (!pcie->appl_res) {\n@@ -2356,6 +2373,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)\n \tif (!pcie->link_state)\n \t\treturn 0;\n \n+\tclk_disable_unprepare(pcie->core_clk_m);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n \n", "prefixes": [ "V5", "8/9" ] }