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GET /api/patches/2194372/?format=api
{ "id": 2194372, "url": "http://patchwork.ozlabs.org/api/patches/2194372/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180936.2026329-5-mmaddireddy@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-5-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:31", "name": "[V5,4/9] PCI: tegra194: Enable DMA interrupt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f697ae92202204045e9d7c338b78e943a444299e", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180936.2026329-5-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491431, "url": "http://patchwork.ozlabs.org/api/series/491431/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491431", "date": "2026-02-08T18:09:29", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491431/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194372/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194372/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-46960-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,4/9] PCI: tegra194: Enable DMA interrupt", "Date": "Sun, 8 Feb 2026 23:39:31 +0530", "Message-ID": "<20260208180936.2026329-5-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tY4RNEoIzdJSbxdZ81p7lAts9WGa63XxW5sdbP50YA69DGFSC9eZnt1iYwAxfwePPEgulXzmLsMn7ief7ZEDnxK9osxKkq6p3exmvOrVDbgxlr2R++q7eNDYIlADzKsHgn6i1iymWa7EFL6DeJp6H7hdx0ySCXBlo8Iwt9nLkhHji3yfontIFjzkfGYP+BMx4tQ9VcNKRUHHbSWi277v+n82LS27ONHNTeMWWrtLh4ucgqamyl2mkJURZENKvlgri/jGSDy+mJUzM5PC61oFkx7I9roHm3TrXZjXCE5UwoQof6O5LM0oVWkWoVs5p4CFnMMX3DqFY5SKWq986FiGtae4yZt4mcooXwD2Cy0gnyeWKJQ41Kusiqd3nqD8tK8FdV1kSCFC8rX+GkWWYIhM/t3MHUgcLzbqXTkAsZX5wym+dAcR8RRoH5RRH0Mblmfzl", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:10:40.9492\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2b4b4105-c714-48ba-d348-08de673d5e97", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW6PR12MB8662" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nEnable DMA interrupt to support Tegra PCIe DMA in both Root port and\nEndpoint modes.\n\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex aeec5f8b9842..110f2adb74d2 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -91,6 +91,7 @@\n #define APPL_INTR_EN_L1_8_0\t\t\t0x44\n #define APPL_INTR_EN_L1_8_BW_MGT_INT_EN\t\tBIT(2)\n #define APPL_INTR_EN_L1_8_AUTO_BW_INT_EN\tBIT(3)\n+#define APPL_INTR_EN_L1_8_EDMA_INT_EN\t\tBIT(6)\n #define APPL_INTR_EN_L1_8_INTX_EN\t\tBIT(11)\n #define APPL_INTR_EN_L1_8_AER_INT_EN\t\tBIT(15)\n \n@@ -547,6 +548,13 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)\n \t\tspurious = 0;\n \t}\n \n+\tif (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {\n+\t\tstatus_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);\n+\t\t/* Interrupt is handled by dma driver, don't treat it as spurious */\n+\t\tif (status_l1 & APPL_INTR_STATUS_L1_8_0_EDMA_INT_MASK)\n+\t\t\tspurious = 0;\n+\t}\n+\n \tif (spurious) {\n \t\tdev_warn(pcie->dev, \"Random interrupt (STATUS = 0x%08X)\\n\",\n \t\t\t status_l0);\n@@ -766,6 +774,7 @@ static void tegra_pcie_enable_intx_interrupts(struct dw_pcie_rp *pp)\n \tval |= APPL_INTR_EN_L1_8_INTX_EN;\n \tval |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;\n \tval |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;\n+\tval |= APPL_INTR_EN_L1_8_EDMA_INT_EN;\n \tif (IS_ENABLED(CONFIG_PCIEAER))\n \t\tval |= APPL_INTR_EN_L1_8_AER_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L1_8_0);\n@@ -1789,6 +1798,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval |= APPL_INTR_EN_L0_0_SYS_INTR_EN;\n \tval |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;\n \tval |= APPL_INTR_EN_L0_0_PCI_CMD_EN_INT_EN;\n+\tval |= APPL_INTR_EN_L0_0_INT_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L0_0);\n \n \tval = appl_readl(pcie, APPL_INTR_EN_L1_0_0);\n@@ -1796,6 +1806,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;\n \tappl_writel(pcie, val, APPL_INTR_EN_L1_0_0);\n \n+\tval = appl_readl(pcie, APPL_INTR_EN_L1_8_0);\n+\tval |= APPL_INTR_EN_L1_8_EDMA_INT_EN;\n+\tappl_writel(pcie, val, APPL_INTR_EN_L1_8_0);\n+\n \t/* 110us for both snoop and no-snoop */\n \tval = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;\n \tval |= (val << LTR_MST_NO_SNOOP_SHIFT);\n", "prefixes": [ "V5", "4/9" ] }