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Show a patch.
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Update a patch.
GET /api/patches/2194367/?format=api
{ "id": 2194367, "url": "http://patchwork.ozlabs.org/api/patches/2194367/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-6-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-6-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:32", "name": "[V5,5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "514303ab0a680b12a56fa893df8e5107941846cf", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-6-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491430, "url": "http://patchwork.ozlabs.org/api/series/491430/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491430", "date": "2026-02-08T18:09:27", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491430/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194367/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194367/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11872-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint", "Date": "Sun, 8 Feb 2026 23:39:32 +0530", "Message-ID": "<20260208180936.2026329-6-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tFdEEJ9CIVtyrrI2/4rRyrdG+Ko4R4+g0S3cY701BA5B/v6acRJq53hxD4L7gLeXHNlZxJjSxH2GzMlIadqh6V7b8I42i9M7ytrCPft0Ybp8yftfJ5RXbCtUobtTISX4IC+RDU7A6qSTju9NtWA5dFpH//cvkUM4TEiJNA94XG4S6jkkxDG+yfTKYZWaKWUMeSguOZ+pR+KCR9tvbzQxGUakLLuobkhQqZaWGqVoLuyOk/Ixjee6nYubWVvml3DwL4a11YHuGcS5oPSBn1HwWDe61atNUCNo7oFprSHb2haq09+ZD/BS5Cw5Ns+JgbohcrJXm9tR+xU6BUApCzXyavbfabnYqj8FtRlUAve5w9duX5nxfBBgx92nqvwyzP3SrxqYfdXYN6DtF+t6jl0lEegDN2D/bVn2TBvk7gz1plSyA3zI18A0JEt5TCWmd/ar6", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:10:36.3826\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 36dc0d86-167d-47d7-8100-08de673d5bcf", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D7.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB9528" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nWhen PCIe link goes down, hardware can retrain the link and try to link up.\nTo enable this feature, program the APPL_CTRL register with hardware hot\nreset with immediate LTSSM enable mode.\n\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 110f2adb74d2..f6305a880cad 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1775,6 +1775,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval = appl_readl(pcie, APPL_CTRL);\n \tval |= APPL_CTRL_SYS_PRE_DET_STATE;\n \tval |= APPL_CTRL_HW_HOT_RST_EN;\n+\tval &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);\n+\tval |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);\n \tappl_writel(pcie, val, APPL_CTRL);\n \n \tval = appl_readl(pcie, APPL_CFG_MISC);\n", "prefixes": [ "V5", "5/9" ] }