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GET /api/patches/2194356/?format=api
{ "id": 2194356, "url": "http://patchwork.ozlabs.org/api/patches/2194356/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-10-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-10-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:36", "name": "[V5,9/9] PCI: tegra194: Add ASPM L1 entrance latency config", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "af014b6444ced81d6f8c23ce723fb479d5fc2c29", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-10-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491430, "url": "http://patchwork.ozlabs.org/api/series/491430/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491430", "date": "2026-02-08T18:09:27", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491430/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194356/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194356/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11876-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,9/9] PCI: tegra194: Add ASPM L1 entrance latency config", "Date": "Sun, 8 Feb 2026 23:39:36 +0530", "Message-ID": "<20260208180936.2026329-10-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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6b4d5fc7-26ab-48f7-487a-08de673d68c6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ1PEPF000023D4.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB9069" }, "content": "For Tegra234, the HW PHY team conducted experiments and determined the\noptimal ASPM L1 entrance latency values: 8 us for Root Port mode and\n16 us for Endpoint mode. Update the default ASPM L1 entrance latency\nconfiguration accordingly.\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 82e9ef172de1..1b4fc6a9bed1 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -244,6 +244,8 @@ struct tegra_pcie_dw_of_data {\n \tu32 cdm_chk_int_en_bit;\n \tu32 gen4_preset_vec;\n \tu8 n_fts[2];\n+\t/* L1 Latency entrance values(Rest/Prod) */\n+\tu32 aspm_l1_enter_lat;\n };\n \n struct tegra_pcie_dw {\n@@ -714,6 +716,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)\n \tval = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);\n \tval &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;\n \tval |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);\n+\tval &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;\n+\tval |= (pcie->of_data->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);\n \tval |= PORT_AFR_ENTER_ASPM;\n \tdw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);\n }\n@@ -2471,6 +2475,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {\n \t/* Gen4 - 5, 6, 8 and 9 presets enabled */\n \t.gen4_preset_vec = 0x360,\n \t.n_fts = { 52, 52 },\n+\t.aspm_l1_enter_lat = 3,\n };\n \n static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {\n@@ -2480,6 +2485,7 @@ static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {\n \t/* Gen4 - 5, 6, 8 and 9 presets enabled */\n \t.gen4_preset_vec = 0x360,\n \t.n_fts = { 52, 52 },\n+\t.aspm_l1_enter_lat = 3,\n };\n \n static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {\n@@ -2492,6 +2498,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {\n \t/* Gen4 - 6, 8 and 9 presets enabled */\n \t.gen4_preset_vec = 0x340,\n \t.n_fts = { 52, 80 },\n+\t.aspm_l1_enter_lat = 4,\n };\n \n static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {\n@@ -2504,6 +2511,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {\n \t/* Gen4 - 6, 8 and 9 presets enabled */\n \t.gen4_preset_vec = 0x340,\n \t.n_fts = { 52, 80 },\n+\t.aspm_l1_enter_lat = 5,\n };\n \n static const struct of_device_id tegra_pcie_dw_of_match[] = {\n", "prefixes": [ "V5", "9/9" ] }