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GET /api/patches/2194350/?format=api
{ "id": 2194350, "url": "http://patchwork.ozlabs.org/api/patches/2194350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180936.2026329-3-mmaddireddy@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-3-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:29", "name": "[V5,2/9] PCI: tegra194: Calibrate P2U for endpoint mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bf565e381cd944ff5e0ff6137821eac3b9512289", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260208180936.2026329-3-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491431, "url": "http://patchwork.ozlabs.org/api/series/491431/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491431", "date": "2026-02-08T18:09:29", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491431/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194350/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194350/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-46957-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,2/9] PCI: tegra194: Calibrate P2U for endpoint mode", "Date": "Sun, 8 Feb 2026 23:39:29 +0530", "Message-ID": "<20260208180936.2026329-3-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\taXw5wcSCGSC9Dn5nSlrNK8JGTDrNvvMns/kA3Fe5otoYERP7gd+MLJNoKtXyO37t14XxlAHEdqxZ4n+HsowYoPMeJQnEZRXf8fJihHLNO/OjriI4pJ1XAJDF7E6n2/RSdv+QNYF1qz+iVRUL8/J4pIFHDp2j+l4/wxSNthrXiZPS9EbomzUZM/YA5BRkYUYgwZhkWXcU0KNqk5QJdp3xHJ9aZ011elzOsUt021RT1f+whLqIT2Fs2KZj+OmTh1aryed6xTovqRx0LVIEgQ8iGWq6NYH92QhMUpiDFptMWfOUko3bZdLVvQ1Fr5VVUjsmXMPfFUmBNuxZU6QwpcRrXoXg9/9dlRlv98UDnnZVt4cFnlZfnQaFjheOIsIY2qPlXSpI4STXEwXcFbV5I7JoHiCpRWoIlFTVcQP/0YQJH3AhMy2Uf076xwtPYeIJojB3", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:10:28.9812\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8f7b642f-db47-40e9-bbad-08de673d5776", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E7.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB5839" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nCalibrate P2U for endpoint controller to request UPHY PLL rate change to\nGen1 during initialization. This helps to reset stale PLL state from the\nprevious bad link state.\n\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++\n 1 file changed, 3 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex f026af7c2ce0..51bad99cec31 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1058,6 +1058,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)\n \t\tret = phy_power_on(pcie->phys[i]);\n \t\tif (ret < 0)\n \t\t\tgoto phy_exit;\n+\n+\t\tif (pcie->of_data->mode == DW_PCIE_EP_TYPE)\n+\t\t\tphy_calibrate(pcie->phys[i]);\n \t}\n \n \treturn 0;\n", "prefixes": [ "V5", "2/9" ] }