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GET /api/patches/2194347/?format=api
{ "id": 2194347, "url": "http://patchwork.ozlabs.org/api/patches/2194347/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-2-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208180936.2026329-2-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-02-08T18:09:28", "name": "[V5,1/9] PCI: tegra194: Drive CLKREQ signal low explicitly", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fa3b070892c12ab214e8b6d0db1ae6656b482c77", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260208180936.2026329-2-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 491430, "url": "http://patchwork.ozlabs.org/api/series/491430/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=491430", "date": "2026-02-08T18:09:27", "name": "Enhancements to pcie-tegra194 driver", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491430/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2194347/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2194347/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11869-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, \"Manikanta\n Maddireddy\" <mmaddireddy@nvidia.com>", "Subject": "[V5,1/9] PCI: tegra194: Drive CLKREQ signal low explicitly", "Date": "Sun, 8 Feb 2026 23:39:28 +0530", "Message-ID": "<20260208180936.2026329-2-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "References": "<20260208180936.2026329-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": 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"X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tEOG15wqsiDVUEXkx0WVJ+FxFpsBkMefZPVHO3pP10zeUqbMJt9gz+nUZ0DVkdL7b7a92+rN6GqEenZgsjkbgJF9AmjTjgyRhiGfR+csXcYy3zz+gLZl5fiDsF+DD/HW2yRYTgk+735v1MPcSt+OmnK8Nds4pndbFv59DARIZ7ZjBLqq1KAYND+BZ++XylhMTvgGb7v00AerqfsgSjxC/l8OZ2tyZfDhUD0+tB/lhM9CppByI9q2rzPnLUHy9h+zWOJLZzoS1/vIj+eVo/rDJNV/ETH9Ui5p9o/jgTQlB7xFvOm9I0z/WpR6m4MQjMc4vz+iGpTcYvAk3ztP2r/iwJ5i0NvUuQVF649rPSFE0mIJcBgoE6HzIBYEgymc47l0it/ZzOp8XnGqvQQMp6XoyLZdsuQI1yiT43dR8fes0cEEy3qeSHJugvyJEVv48LZxL", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Feb 2026 18:10:12.1856\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b3a165da-b699-4b5d-ccb8-08de673d4d75", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMWH0EPF000971E8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB7590" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nCurrently, the default setting is that CLKREQ signal of a Root Port\nis internally overridden to '0' to enable REFCLK to flow out to the slot.\nIt is observed that one of the PCIe switches (case in point Broadcom PCIe\nGen4 switch) is propagating the CLKREQ signal of the root port to the\ndownstream side of the switch and expecting the endpoints to pull it low\nso that it (PCIe switch) can give out the REFCLK although the Switch as\nsuch doesn't support CLK-PM or ASPM-L1SS. So, as a workaround, this patch\ndrives the CLKREQ of the Root Port itself low to avoid link up issues\nbetween PCIe switch downstream port and endpoints. This is not a wrong\nthing to do after all the CLKREQ is anyway being overridden to '0'\ninternally and now it is just that the same is being propagated outside\nalso.\n\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nV5:\n* None\n\nV4:\n* None\n\nV3:\n* None\n\nV2:\n* None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 9883d14f7f97..f026af7c2ce0 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -44,6 +44,7 @@\n #define APPL_PINMUX_CLKREQ_OVERRIDE\t\tBIT(3)\n #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN\tBIT(4)\n #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE\tBIT(5)\n+#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE\tBIT(13)\n \n #define APPL_CTRL\t\t\t\t0x4\n #define APPL_CTRL_SYS_PRE_DET_STATE\t\tBIT(6)\n@@ -1415,6 +1416,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,\n \t\tval = appl_readl(pcie, APPL_PINMUX);\n \t\tval |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;\n \t\tval &= ~APPL_PINMUX_CLKREQ_OVERRIDE;\n+\t\tval &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;\n \t\tappl_writel(pcie, val, APPL_PINMUX);\n \t}\n \n", "prefixes": [ "V5", "1/9" ] }